Applied Materials, Inc.

Terry P Reiss

Arulkumar P Shanmugasundram

Dimitris Lymberopoulos

Alexander T Schwarm

Michael E Wilmer

Natalia Kroupnova

Sherry Cordova

Yukari Nishimura

Clari Nolet

Richard C Lyon

Woon Young Toh

Terry Lee Doyle

Evgueni Lobovski

Inna Louneva

Stefanie Harvey

Semiconductor wafers are processed in conjunction with a manufacturing execution system using a run-to-run controller and a fault detection system. A recipe is received from the manufacturing execution system by the run-to-run controller for controlling a tool. The recipe includes a setpoint for obtaining one or more target wafer properties. Processing of the wafers is monitored by measuring processing attributes including fault conditions and wafer properties using the fault detection system and one or more sensors. Setpoints of the recipe may be modified at the run-to-run controller according to the processing attributes to maintain the target wafer properties, except in cases when a fault condition is detected by the fault detection system. Thus, data acquired in the presence of tool or wafer fault conditions are not used for feedback purposes. In addition, fault detection models may be used to define a range of conditions indicative of a fault condition. In these cases, the fault detection models may be modified to incorporate, as parameters, setpoints of a recipe modified by a run-to-run controller.

Integration of fault detection with run-to-run control

The present invention provides a semiconductor processing device () including a tool () having one or more sensors, a primary data communication port () and a secondary data communication port (). A sensor data acquisition subsystem () acquires sensor data from the tool via the secondary port (). The data acquisition subsystem () acquires MES operation messages via the primary port (). Sensor data are communicated to a sensor processing unit () of a sensor data processing subsystem (). The sensor processing unit () processes and analyzes the sensor data. Additionally, the processing unit () can be adapted for making product or processing related decisions, for example activating an alarm if the process is not operating within control limits. In another embodiment, the present invention provides a method and apparatus for processing data from a wafer fab facility () including a plurality of tools () each having a primary data communication port () and a secondary data communication port ().

Wafer fabrication data acquisition and management systems

Fault detection of a semiconductor processing tool employs several techniques to improve accuracy. One technique is sensor grouping, wherein a fault detection index is calculated from a group of tool operational parameters that correlate with one another. Another technique is sensor ranking, wherein sensors are accorded different weights in calculating the fault detection index. Improved accuracy in fault detection may be accomplished by employing a variety of sensor types to predict behavior of the semiconductor processing tool. Examples of such sensor types include active sensors, cluster sensors, passive/inclusive sensors, and synthetic sensors.

Fault detection and virtual sensor methods for tool fault monitoring

Run-to-run variation of a semiconductor fabrication tool is minimized utilizing a mirror image target. A goal represents a process result desired from operation of the tool. The mirror image target is generated by adding the goal to a difference between an output from a previous tool run and the goal. Prediction of tool performance is based upon a data-based modeling engine utilizing a reference library correlating operational parameters with observed process results for prior tool runs. The mirror image target vector is compared to the reference library and serves as a basis for generating the recipe for the subsequent process run. This recipe automatically brings operation of the tool back toward the goal. The method may further include comparison of the suggested recipe with the recipe of the prior run to determine whether run-to-run variation is serious enough to warrant a change in tool conditions, or whether run-to-run variation is so serious as to indicate a major tool problem. Generation of the mirror image target, and utilization of the mirror image target to create a new process recipe, eliminates effort and uncertainty associated with conventional nonsystematic analysis of tool variation, followed by manual intervention by the operator to adjust tool parameters to reduce such variation.

Run-to-run control over semiconductor processing tool based upon mirror image target

A methodology is provided for qualitatively identifying features of an article, such as defects on the surface of a semiconductor substrate, with a string of symbols, such as numbers, according to relevant defect characteristics and information relating to the processing tools visited by the wafer, including reliability information. Embodiments include generalizing, after a defect on a wafer is discovered and inspected (as by optical review, SEM, EDS, AFM, etc.), each quantitative attribute of the defect such as the defect's size, material composition, color, position on the surface of the wafer, etc. into a qualitative category, assigning a numerical symbol to each attribute for identification, and sequencing the symbols in a predetermined manner. The identification sequences of all defects are stored in a database, where they are easily compared with other correspondingly identified defects. The identification sequence also includes a number representative of the wafer's last-visited processing tool, thereby associating the defect with a tool. After the defect is investigated and determined as being caused by a particular fault of the tool, this information is stored and linked to the defect's identification sequence. Thereafter, if a similar defect occurs in another wafer, the later defect's identification sequence is matched to that of the previous defect by searching the defect database, indicating the same cause for the later defect, thereby enabling ready identification of the root causes of defects, and enabling early corrective action to be taken.

Defect reference system automatic pattern classification

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San Jose, CA, United States of America

Terry P Reiss