Micron Technology Incorporated

Microsoft Technology Licensing, LLC

Intel Corporation

Other

Lodestar Licensing Group LLC

Terry M Grunzke

Ali Mohammadzadeh

Jung Sheng Hoei

Dheeraj Srinivasan

Brett Kenneth Dodds

Ryan G Fisher

Majid Anaraki Nemati

Sivagnanam Parthasarathy

Luca De Santis

Renato C Padilla

Walter Di Francesco

Gianfranco Valeri

Lucia Botticchio

Jeffrey M Tsai

Vamshi K Indavarapu

Tommaso Vali

Dean K Nobunaga

Umberto Siciliani

Mark A Hawes

Rahul Mitchell Jairaj

Timothy B Cowles

June Lee

Ali Ghalam

The described technology provides a multi-level error correction method, including encoding data received from a double data rate (DDR) memory by performing primary coding to generate transitional symbols, wherein the primary coding comprising at least one of cyclical redundancy check (CRC) encoding and single error correction double error detection (SECDED) encoding, performing a secondary coding on the transitional symbols to generate inner codes, the inner codes comprising code 1 parities generated from the transitional symbols and code 2 parities generated from the transitional symbols and metadata stored on the DDR memory, wherein the secondary coding comprising Reed Solomon (RS) encoding, and saving the inner codes on parity bit storage locations on a die of the DDR memory.

Error correction using on-die parity bit storage and transitional signals

A method, computer program product, and computing system for generating first encoded data by performing a first encoding of data included within each of a plurality of memory dies of a memory module using an exclusive-or (XOR) encoding process. Second encoded data is generated by performing a second encoding of the data included within each of the plurality of memory dies of the memory module and the first encoded data using a cyclic code encoding process. Error correction is performed on the data included within each of the plurality of memory dies of the memory module using the first encoded data, the second encoded data, an XOR decoding process, and a cyclic code error correction process.

System and method for protecting data using cyclic properties of error correcting code

A method, computer program product, and computing system for defining one or more groups for data included within one or more groups of memory dies included within a memory module, thus defining a first group of parity bit groups; defining a parity bit for each memory die included within the one or more groups of memory dies, thus defining a plurality of parity bits; and defining one or more parity bit groups for the plurality of parity bits, thus defining a second group of parity bit groups.

Low complexity system and method for detection and correction of data with additional metadata from corruption

A method, computer program product, and computing system for defining one or more encoded symbols for data included within each of a plurality of memory dies of a memory module to define one or more groups of encoded symbols; generating Reed-Solomon parities for each group of encoded symbols; and recovering one or more portions of the data included within each of the plurality of memory dies of the memory module in the event of data corruption or die failure using one or more of the encoded symbols and the Reed-Solomon parities.

System and method for protecting data

A memory controller may receive memory data to be stored on a memory. A memory controller may receive metadata related to the memory data. The metadata may be selected from a predetermined list of metadata. A memory controller may identify an encoding polynomial of a plurality of polynomials that is associated with the metadata, each polynomial of the plurality of polynomials associated with different metadata from the predetermined list of metadata. A memory controller may generate a codeword using the encoding polynomial of the plurality of polynomials and the memory data.

Devices, systems, and methods for encoding and decoding codewords

Apparatus might include a first plurality of signal lines, a second plurality of signal lines, a controller, a first die, and a second die. The controller, the first die, and the second die might each be connected to the first plurality of signal lines and connected to the second plurality of signal lines. The first die and the second die might each include termination circuitry connected to a particular signal line of the second plurality of signal lines. The first die might be configured to activate its termination circuitry in response to receiving a particular combination of signal values on the first plurality of signal lines. The second die might be configured to deactivate its termination circuitry in response to receiving the particular combination of signal values on the first plurality of signal lines.

Apparatus having selectively-activated termination circuitry

Devices and techniques to recover data from a memory device are disclosed, including recovering data corresponding to a detected error in data stored on a memory array corresponding to a memory operation using one of a set of read offset values and loading the one of the set of read offset values used to recover data corresponding to the detected error in a temporary storage of the memory array as a custom read offset value for a subsequent memory operation. The temporary storage of the memory array can include a scratch space of the memory array separate from read retry offset registers of the memory device.

Read retry scratch space

Disclosed are examples of apparatuses including memory devices and systems comprising memories sharing a common enable signal, wherein the memories may be put into different power modes. Example methods for setting the different power modes of the memories are disclosed. In some examples, different power modes may be set by issuing memory group-level commands, memory-level commands, or combinations thereof.

Apparatuses and methods of entering unselected memories into a different power mode during multi-memory operation

Devices and techniques to recover data from a memory device using a custom Read Retry feature are disclosed herein. A memory device can receive a first read request, read data from the memory array corresponding to the read request, and determine if the read data corresponding to the first read request includes a detectable error. In response to a detected error in the received data corresponding to the first read request, the memory device can recover data corresponding to the first read request using one of a set of read retry features, and load the one of the set of read retry features used to recover data corresponding to the first read request as a custom read retry feature in the memory device for a second read request subsequent to the first read request.

The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.

Apparatuses and methods to control memory operations on buffers

The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

Partially written block treatment

Memory devices might include an input/output (I/O) node, a termination device, an array of memory cells in communication with the I/O node through the termination device, and control circuitry, wherein the control circuitry is configured to compare an address received by the memory device to a plurality of instances of address information stored in the memory device. Each instance of address information of the plurality of instances of address information might correspond to a respective termination value stored in the memory device. In response to the memory device receiving an address matching an instance of address information stored in the memory device, the control circuitry might further be configured to activate the termination device using the respective termination value corresponding to the instance of address information matching the received address.

Memory devices having selectively-activated termination devices

An example apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.

Apparatuses and methods for automated dynamic word line start voltage

Memory devices including a controller for access of an array of memory cells that is configured to accept a sequence of commands to cause the memory device to read a first set of data from the array of memory cells into a first register, load the first set of data into a first portion of a second register, write a set of test data to a second portion of the second register during a reading of a second set of data from the array of memory cells to the first register, read the set of test data from the second portion of the second register during the reading of the second set of data, and output the set of test data from the memory device during the reading of the second set of data.

Memory devices configured to test data path integrity

A volatile memory device is configured to self-document by identifying its own bad or at-risk excludable memory locations in a nonvolatile identification embedded in itself, without using additional board real estate. The identification of bad or at-risk memory is readable by firmware outside the device. The device includes volatile memory cells that have respective failure susceptibility values, some of which indicate bad or at-risk memory cells. The memory device also includes read logic and write logic, and may include refresh logic. The identification may be embedded in the device by blowing fuses in an adaptation of self-repair activity, or by writing identification data into a serial presence detect logic, for example. The configured memory device may efficiently, persistently, and reliably provide detailed memory test results regarding itself, thereby allowing customers to accept and safely use memory that would otherwise have been discarded to prevent software crashes.

Growing community of inventors

Boise, ID, United States of America

Terry M Grunzke