Intel Corporation

Terry M Fletcher

Edward Costales

David Wyatt

Barnes Cooper

Rajesh Bhikhubhai Patel

Andrew W Martwick

William A Stevens, Jr

Belliappa Manavattira Kuttanna

Ashish V Choubal

Lance E Hacking

Binta M Patel

Matt King

Steven Scott Varnum

Embodiments of systems, apparatuses, and methods for correcting double bit burst errors using a low density parity check technique are disclosed. In one embodiment, an apparatus includes an encoder to generate a parity vector by multiplying a first version of a data vector by a matrix. The parity vector is to identify correctable double-bit burst errors in a second version of the data vector. The apparatus also includes logic to concatenate the parity vector and the first version of the data vector.

Correcting double-bit burst errors using a low density parity check technique

Systems and methods provide automatic switching of display update properties such as screen resolution, pixel depth, and refresh rate in response to a power management event. The display update property may be decreased when power is switched from AC power to DC power, for example, when the system is unplugged from a wall outlet and is running on battery power.

Switching display update properties upon detecting a power management event

A method, device, and system are disclosed. In one embodiment the method includes causing a processor to enter into a first power state. Then an interrupt is received that signals the processor to leave the first power state. The method continues by causing the processor to remain in the first power state if the interrupt was received less than a minimum dwell time after the processor entered the first power state.

Method, device, and system for guaranteed minimum processor power state dwell time

A method to reduce idle leakage power in I/O pins of an integrated circuit using external circuitry. Initially, I/O pins on a package are subdivided into those that will also remain powered up and those that will power down during idle state. When a system enters a low power mode, a signal is sent to the external circuitry. The signal notifies the I/O pins that always remain powered up to notify the external circuitry to power down the other set of I/O pins.

Reducing idle leakage power in an IC

A processor-based system includes a system firmware program that is transferred to a designated region of a memory in response to an initialization (e.g., a boot sequence). When initialized, for example using at least one programmable register, the system firmware program reconfigures the memory from a first configuration (i.e., a default state) to a second configuration to receive a pattern. By changing the memory to the second configuration, the memory may be declared to be a write combining type. For storage into the memory, the pattern may be buffered in one or more data blocks. Once the pattern is stored, the memory may be restored to the first configuration. Buffered data transfers of the pattern may selectively clear the memory thus providing a rapid booting of the processor-based system.

Reconfiguring memory to reduce boot time

A method and apparatus are provided for obtaining throttle settings of a system, such as a chipset. A first bandwidth may be applied to a first area (or interface) of the system and a temperature of the first area may be sensed using a thermal sensor. The bandwidth passing through this first area may be increased or decreased based on the sensed temperature to obtain an ideal or optimized setting.

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Sacramento, CA, United States of America

Terry M Fletcher