Texas Instruments Corporation

Ess Technology, Inc.

Terry Lee Sculley

Arup Polley

Leonardo William Estevez

Shawn Xianggang Yu

Mark Stephen Toth

Christian Link

Xianggang Yu

Scott Robert Summerfelt

Wei-Yan Shih

Alok Kumar Lohia

Steve Kummerl

Russell Melvin Rosenquist

Seung Bae Lee

Daryl G Sartain

Srinath Mathur Ramaswamy

Ganesan Thiagarajan

Timothy F Murphy

Srinadh Madhavapeddi

Jung-Kuei Chang

Edmund Chui

Jeffrey Alan Niehaus

Shawn Xianggang

A method includes pulsating a magnetic field at a first location associated with an external surface of a wall containing magnetic material. The method also includes measuring at least one characteristic of the pulsating magnetic field at a second location associated with the external surface of the wall. The at least one characteristic changes based on corrosion on an internal surface the wall between the first and second locations. The magnetic field could be pulsated by applying an AC signal to a conductive coil or by vibrating a magnet. The method could also include analyzing the at least one measured characteristic to identify an amount of the corrosion and/or a change in the amount of the corrosion. Use of the internal surface the wall could be modified based on the amount or change of the corrosion.

Surface sensing method for corrosion sensing via magnetic modulation

An integrated force sensing element includes a piezoelectric sensor formed in an integrated circuit (IC) chip and a strain gauge at least partially overlying the piezoelectric sensor, where the piezoelectric sensor is able to flex. A human-machine interface using the integrated force sensing element is also disclosed and may include a conditioning circuit, temperature gauge, FRAM and a processor core.

Piezoelectric sensor apparatus

A system includes a battery and a monitoring circuit coupled to the battery. The monitoring circuit includes a sense circuit and a peripheral device coupled to the sense circuit. The peripheral device includes a universal asynchronous receiver-transmitter (UART) receiver having an adaptive sample timing circuit with a numerically-controlled oscillator (NCO) circuit. The peripheral device also includes memory coupled to the UART receiver and configured to store battery monitoring data.

UART receiver with adaptive sample timing control using a numerically-controlled oscillator

A method includes pulsating a magnetic field at a first location associated with an external surface of a wall containing magnetic material. The method also includes measuring at least one characteristic of the pulsating magnetic field at a second location associated with the external surface of the wall. The at least one characteristic changes based on corrosion on an internal surface the wall between the first and second locations. The magnetic field could be pulsated by applying an AC signal to a conductive coil or by vibrating a magnet. The method could also include analyzing the at least one measured characteristic to identify an amount of the corrosion and/or a change in the amount of the corrosion. Use of the internal surface the wall could be modified based on the amount or change of the corrosion. Multiple magnetic fields can be generated at multiple first locations, and the at least one characteristic can be measured at multiple second locations.

An integrated force sensing element includes a piezoelectric sensor formed in an integrated circuit (IC) chip and a strain gauge at least partially overlying the piezoelectric sensor, where the piezoelectric sensor is able to flex. A human-machine interface using the integrated force sensing element may include a conditioning circuit, temperature gauge, FRAM and a processor core.

Integrated force sensing element

A system for measuring current includes a conductive trace comprising N substantially parallel straight sections having a substantially constant cross-section, N&#x2265;4. Adjacent substantially straight sections are spaced apart by a given distance and each pair of adjacent straight sections is connected by a respective loop of the current trace such that current in odd-numbered straight sections flows in a first direction and current in even-numbered straight sections flows in an opposite direction. The N magnetic field based current sensors are each positioned on a respective straight section of the conductive trace. The current is calculated based on where M=N&#x2212;1, and S(i) is the measured signal read at magnetic field based current sensor i.

Removal of higher order magnetic interference in magnetic field based current sensors

A closed-loop calibration scheme is configured to allow a device to remain in continuous operation. A signal generator device provides a pseudorandom sequence for a signal received by a magnetic field magnetic field sensor, such as a Hall-effect sensor. A signal decoder circuit receives the output signal and decouples the generated spread spectrum signal from the interference by measuring the gain in the overall signal. The decoder device distinguishes the known spread spectrum signal from any perturbation effects of particular bandwidths. A processing circuit then outputs a signal that has an operation parameter that has been adjusted to compensate for the perturbation effects. The processing circuit provides the receiver circuit with the compensation signal, hence forming a closed-loop calibration configuration.

Closed-loop device calibration using a wideband signal

Operating a current sensor by conducting a current serially through a first region and a second region of an electrically conductive member. A first magnetic field produced by the current in the first region is sensed using a first magnetic field based current (MFBC) sensor having a first sensitivity. The sensitivity of a second MFBC is reduced. A second magnetic field produced by the current in the second region is sensed using the second MFBC sensor having a reduced sensitivity, in which the reduced sensitivity is lower than the first sensitivity. A magnitude of the current is calculated based on the first magnetic field and the second magnetic field. A dynamic range of the current sensor is extended by calculating a magnitude of the current using the second magnetic field after the first MFBC is saturated.

Fluxgate-based current sensor

Methods and apparatus for magnetic sensors and integrated calibration. In an example arrangement, a system includes a magnetic sensor configured to output a signal corresponding to magnetic fields; a calibration trace disposed proximal to the magnetic sensor; a controlled current source coupled to the calibration trace and configured to output a current resulting in a magnetic field output from the calibration trace; and a comparator coupled to the output signal from the magnetic sensor and to an expected signal. In the example arrangement, the comparator outputs a signal indicating whether the output signal from the magnetic sensor corresponds to the expected signal. Methods are also disclosed.

Methods and apparatus for magnetic sensor with integrated calibration mechanism

In recent years, it has become commonplace for portable devices to generate analog audio signals from numerous sources, meaning that the codecs employed in these portable devices need to be able to utilize various digital bit streams at different sampling rates. To date, however, the circuitry for asynchronous sampling rate conversions for multiple bit streams has been complex, rigid, and power hungry. Here, a codec is provided which uses miniDSP cores to perform asynchronous sampling rate conversion efficiently and with reduced power consumption compared to other conventional codecs.

Asynchronous sampling rate converter for audio applications

A clock signal generator () includes a phase locked loop (PLL) circuit () which requires a reference clock signal of at least a predetermined first frequency (f). A first clock signal (REFCLK) of a second frequency (f) that is substantially lower than the first frequency (f) is multiplied so as to produce a second clock signal (DIGCLK) which has a frequency at least as high as the first frequency (f) and which is phase-locked with respect to the first clock signal (REFCLK). The second clock signal (DIGCLK) is applied to a reference signal input of the PLL circuit (), which produces an output clock signal (PLLCLK or CLKOUT).

Operating clock generation system and method for audio applications

A low-power data conversion system for converting a serial digital data input signal (DIN) to an analog output signal (Vout) by generating the serial digital data input signal (DIN) at a first sample rate (fsin) in a burst mode, wherein the sampling frequency of the serial digital data input signal (DIN) has a predetermined ratio to the frequency of an external reference clock signal (SLEEPCLK or WCLK). The serial digital data input signal (DIN) is converted into parallel format. A FIFO system temporarily stores a predetermined number of samples (Din) of the parallel format digital data input signal. The samples (Din) have a first sample rate (fsin). The samples (Din) are converted to an analog output signal (Vout).

Low-power high-performance audio DAC system including internal oscillator, FIFO memory, and ASRC

A sample rate converter suitable for use in an audio DAC includes a first estimating circuit (A) generating first (TR) and second (STAMPR) signals synchronized to an asynchronous clock (MCLK) and representing the period and edge arrival times, respectively, of a reference clock (REFCLK). A second estimating circuit (B) operates on the first and second signals to generate third (T) and fourth (STAMP) signals representing an input sample rate (32fsin) and arrival times of input data samples, respectively, which are applied to a coefficient and address generator () to generate read addresses and coefficients input to a FIFO memory () receiving digital input data at the input sample rate and a multiplication/accumulation circuit () receiving data from the FIFO memory. The multiplication/accumulation circuit produces an output signal (SRC-out) synchronized to the asynchronous clock at an output sample rate (32fsout).

Asynchronous sampling rate converter and method for audio DAC

An asynchronous sample rate converter interpolates and filters a digital audio input signal to produce a filtered, up-sampled first signal. A FIFO memory receives the first signal and stores samples thereof at locations determined by a write address and presents stored samples from locations determined by a read address. The presented samples are passed through an interpolation and resampling circuit to produce a continuous-time signal which is re-sampled to produce a signal that is up-sampled relative to a desired output. That signal then is filtered and down-sampled to produce the output signal. Sample rate estimating circuitry computes a difference signal representative of a time at which a data sample of the audio input signal is received and a time at which a corresponding audio output sample is required, and address generation circuitry generates the read and write addresses. A coefficient calculation circuit calculates filter coefficients for the interpolation and resampling circuit in response to the difference signal.

Growing community of inventors

Lewisville, TX, United States of America

Terry Lee Sculley