International Business Machines Corporation

Terry Lee Leasure

George McNeil Lattimore

Gus Wai-Yan Yeung

Robert Anthony Ross, Jr

Michael Kevin Ciraula

Gus Wai-Yen Yeung

Manoj N Kumar

Jose Angel Paredes

John Beck

Philip George Shephard, Iii

Younes John Lotfi

T W Griffith

Gus Wai Yan Yeung

Chi Duy Bui

Kevin Xiaoqiang Zhang

An apparatus and method for unaligned cache reads is implemented. Data signals on a system bus are remapped into a cache line wherein a plurality of data values to be read from the cache are output in a group-wise fashion. The remapping defines a grouping of the data values in the cache line. A multiplexer is coupled to each group of storage units containing the data values, wherein a multiplexer input is coupled to each storage unit in the corresponding group. A logic array coupled to each MUX generates a control signal for selecting the data value output from each MUX. The control signal is generated in response to the read address which is decoded by each logic array.

Apparatus for unaligned cache reads and methods therefor

Each match word line driver circuit associated with a content addressable memory (CAM) utilizes a scannable latch for testing. The scannable latches associated with a particular CAM are connected together, scan output of one to scan input of the next, forming a scanning latch chain. In test mode the scannable dynamic latch is used either for testing CAM match circuits or for driving word lines to test the RAM array. Testing CAM match circuits is accomplished by patterning the CAM array with known storage values. The match circuitry then compares an effective address to each storage value and the results are scanned out. Testing the RAM array is performed by driving each word line with a known scan value. Each word line responds the scan value and a sense amplifier outputs a RAM array value based on the word line.

System and method of generating dynamic word line from the content addressable memory (CAM) &ldquo;hit/miss&rdquo; signal which is scannable for testability

A first latch circuit (,) and a control latch circuit (,) are used to control another circuit (,) in a self-timed circuit arrangement (,). The first latch circuit (,) produces a first latch circuit output signal (L,) responsive to a first clock signal (C,) in a multiple-clock system. The control latch circuit (,) responds to the second clock signal (C,) to latch the first latch output signal (L,) and produce a reset control signal which is used to produce both a reset signal (RE) and a control output signal (L,). The reset signal (RE) resets the first latch circuit (,), while the control output signal (L,) may be used to control the other circuit (,) even after the first latch circuit is reset.

Apparatus and method for controlling a reset in a self-timed circuit of a multiple-clock system

A comparator circuit (,) includes a comparator network and a comparator enabling device (,) and may be integrated with a sense amplifier circuit (,). The comparator network is adapted to receive a complementary pair of reference data signals (B, B,) and a complementary pair of analog data signals (d1, d1b). An output of the comparator circuit (,) represents a comparison of the data represented by the reference data signals and the data represented by the analog data signals. The comparator output is generated in response to a comparator enable signal (SE) applied to the comparator enabling device (,) while the input data is applied to the comparator network. The comparator enable signal (SE) is applied at a time when the analog data signals (d1, d1b) have developed a minimum differential level.

Sense amplifier/comparator circuit and data comparison method

A memory array is modified by segmenting the total length of a bitline into smaller bitline sections referred to as local bitlines. Included is an additional bitline into the array for every bitline that has been segmented. This new bitline is referred to as the global bitline. After segmentation, the array appears as several smaller sub-arrays; each sub-array has fewer cells per segmentation (local bitline) than the sum total of cells along the more traditional non-segmented bitline approach. These smaller sub-arrays (local bitline segmentations) are independent of one another and only one sub-array can be accessed per memory request (read/write). The reduced length and cell count per local bitline within each sub-array substantially reduces the total bitline capacitance (e.g., diffusion capacitance) discharged by a single memory cell during a read operation. Reducing bitline capacitance results in faster signal development and restore time on the bitline; thus, several smaller sub-arrays can be cycled much faster than a single large array.

Memory in a data processing system having improved performance and

A column (10) of a memory array includes a plurality of memory cells (11, 12) each having first and second independent access ports (T1, T2) and a cross-coupled memory latch (20). The first access port (T1) of each memory cell (11, 12) connects a first node (21) of the latch (20) to a first bit line (14), while the second access port (T2) of each memory cell connects a second node (22) of the latch (20) to a second bit line (15). A clearing arrangement (T7) is connected to the second bit line (15) for selectively coupling the second bit line to ground. A write driver is connected to the first bit line (14) for writing data to the memory cells (11, 12) in the form of single-ended signals. A memory cell is placed in a preset condition by simultaneously coupling the second node (22) to the second bit line (15) through the second access port (T2) and coupling the second bit line to ground through the clearing arrangement (T7). Once in the preset condition, data may be written to the cell by coupling the first bit line (14) to the first node (21) through the first access port (T1) and driving data to the first bit line.

Memory array and method for writing data to memory

A set associative cache memory array includes redundant memory portions for use in the case of a defective portion of the memory. Information is stored within the defective portion of the memory array and an identical copy is stored within the redundant portion. Additionally, reading of the information is done from both the defective portion and the redundant portion. Selection of the information from either the defective portion or the redundant portion is made using programmable circuitry such as a fuse.

Redundant memory array

A five transistor memory cell, is a single ended static random access memory (SRAM) cell. Reading and writing from the cell is implemented with one bit line along with word line read and word line write signals. One of the transistors within the memory cell is not coupled directly to ground, but is instead coupled to a controlled impedance node. This permits the affected transistor to float between ground and a high impedance state, which permits one bit line to write into the memory cell.

Memory cell

A device for accessing a specific word line in a memory array has improved noise protection by smoothing out the RC load in the word line mapping circuit. The word lines are respectively connected to rows of memory cells in the memory array, and predecoded word lines are used to decode encoded addresses which correspond to the various rows. The circuit connects the word lines to the predecoded word lines by gates which are tapped into the predecoded word lines, and the taps on a given predecoded word line are non-adjacent, to more evenly distribute the RC delay for each predecoded word line. In other words, the word lines are interspersed, out of order. The word lines can be interspersed randomly, or according to a predetermined function, such as a modulo function. The RC load for a given predecoded word line is preferably uniformly distributed along substantially the entire length of the predecoded word line.

Evenly distributed RC delay word line decoding and mapping

An improved self-restore circuit and method for restoring the output line of a dynamic logic circuit. The self-restore circuit includes two transistors connected in series between the output line and the reference voltage node. The first transistor activates after an evaluation of the output line, while the second transistor only activates subsequent to the activation of the first transistor and the completion of an evaluation cycle. The self-restore circuit reduces the power consumption and safeguards against any soft error hits, wherein the second transistor protects against any soft error hits by actively pulling up the output line to the appropriate voltage.

Self-restore circuit with soft error protection for dynamic logic

According to the present invention, a comparison circuit for combining a plurality of data bits is provided. One version of the invention includes a comparator which provides a signal responsive to a comparison of the voltage states of at least two of the plurality of data bits, and an amplifier which is coupled to the comparator and compares the signal provided by the comparator to a reference voltage to provide an output signal, the reference voltage being between a high and a low voltage state.

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Georgetown, TX, United States of America

Terry Lee Leasure