International Business Machines Corporation

Terry L Weakley

Gaby J Salem

An enhanced microprocessor (278) (FIG. 6) having a first portion (153) (FIG. 7) and a second portion (196) (FIG. 8) configured to eliminate prefetching of instructions from an instruction cache (102) (FIG. 6) when the required instructions are already present within a prefetch buffer (104) (FIG. 6). The first portion (153) and second portion (196) are in circuit communication with a prefetch buffer (104) (FIG. 6), branch target cache (108) (FIG. 6), control unit (110) (FIG. 6), and execution unit (112) (FIG. 6). The first portion (153) is responsive to forward or backward branch instructions that have a branch target within the same prefetch buffer, and to forward branch instructions that have a branch target within a next successive prefetch buffer. The first portion (153) is configured to inhibit prefetching of instructions when such conditions are present. The second portion (196) is responsive to backward branch instructions that have a branch target within an immediately preceding prefetch buffer and configured to assert a prefetch inhibit signal to prevent any further prefetching of instructions.

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Boca Raton, FL, United States of America

Terry L Weakley