National Semiconductor Corporation

Control Data Corporation

Control Data System, Inc.

Terry L Lyon

Dennis L Wendell

Jeff Chritz

Dan Lunecki

Charles Hochstedler

A data cache memory apparatus permits load and store instructions to be issued out-of-order. The apparatus includes a memory. An instruction issue apparatus issues an instruction stream containing store and load instructions. The store instructions are completed in two passes, namely a store allocate pass and a corresponding store commit pass. A cache control is connected to the instruction issue apparatus and the memory and issues store and load addresses to the memory in response to instructions from the instruction issue apparatus. A store history table is connected to the cache control and stores a record of the addresses of the memory where data are to be stored, and thus a record of the store allocate passes issued by the instruction issue apparatus for which no corresponding store commit pass has been completed. The cache control responds to the subsequent corresponding store commit pass to issue the store address to the memory and to clear the store instruction from the store history table. If a load instruction designates an address for which a store allocate pass has issued but the corresponding store commit pass has not yet been issued, the cache control determines a conflict and the load instruction is reissued. Provision is made for retrieving data from a secondary cache and for clearing store instructions from the store history table upon detection of a branch error.

Dual pipe cache memory with out-of-order issue capability

A clock multiplier is selectable to provide either an unmultiplied input clock to the internal clock line or a multiplied clock signal, depending upon the state of a test mode input signal. By providing the circuitry on a integrated circuit chip, the chip can be driven at its normal operating frequency using lower-frequency test equipment. One multiplier device includes a plurality of series-connected one-shots.

Clock signal multiplier

A scan diagnostics apparatus and method is useful in connection with the memory integrated circuit. A shift register is provided which can receive data in parallel from the input register and output the data serially. The shift register can receive serial data and output in parallel either to the input buffer or the output buffer. Preferably the shift register can receive in parallel, data from the output buffer and output the data serially.

Serial scan diagnostics apparatus and method for a memory device

A circuit means for detecting data errors in VLSI processing circuits at the earliest point such an error occurs in the processing stream or (in different modes) at any selected point therein, and for providing the prior operands and faulty (intermediate) output data together with an indication of what is wrong with the data. Described are registers and/or means for controlling the mode of the circuitry, error detection means (being, for example, parity check circuits), and an output means for providing the output in an organized way responsive to the controlling means and the output of the error detecton means. The method of using such a circuit is inherent in the disclosure.

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Roseville, MN, United States of America

Terry L Lyon