Intel Corporation

Other

Terry L Kendall

Richard P Garner

Steven E Wells

Virgil N Kynett

Kenneth G McKee

Sanjay S Talreja

Robert E Larsen

Robert N Hasbun

Sandeep K Guliani

Peter K Hazen

Charles W Brown

Dave M Brown

Collin Ong

Khandker N Quader

Paul D Ruby

Kurt B Robinson

Joseph H Salmon

Deborah L See

Ramkarthik Ganesan

Mark J Christopherson

Terry D West

Kishore Rao

Jason Panavich

James W Bridgewater

A method wherein a special programming mode of a memory is entered and internal program verification by the memory is disabled. An apparatus is also described having a host processor and a memory with special programming mode circuitry. The memory includes automation circuitry for program verification. A plurality of words is programmed into the memory without the memory performing internal program verification. The special programming mode is exited and internal program verification by the memory is enabled. The special programming mode may use hashing to optimize testing for a memory such as a nonvolatile flash memory.

Method and apparatus including special programming mode circuitry which disables internal program verification operations by a memory

A single status register, capable of providing status for simultaneous read-while-write operation on a flash memory array is described. The status of the memory array is reported to the user based on two partitions. A microcontroller is used to traffic the status register to memory array communication.

Status register architecture for flexible read-while-write device

A default configuration for a memory is placed in a non-volatile register, while an input logic circuit can provide at least one alternate programmable configuration. A selection circuit can select between the default configuration and the programmable configuration. The selected configuration can be placed into a register that provides active configuration data that is used to determine the actual memory configuration. Upon a reset condition, a reset configuration bit can be used to determine whether the memory will be reset with the default configuration or the active configuration that was being used before the reset.

System and method for selecting and loading configuration data into a register through the use of a first and second reset signal

A small cache memory can be incorporated with a main memory, such as a flash memory, on an integrated circuit to improve average access times between a processor and the main memory. To minimize cost and complexity, the cache memory may contain only a few words of data. The cache can also allow a suspended transfer with minimal latency when the transfer is resumed. Designing the cache memory to interface with the processor over a standard memory bus permits the cache to be implemented in a system that could otherwise have no cache memory unless the processor and/or memory bus were redesigned.

Flash memory low-latency cache

The present invention is in the field of flash memory. More particularly, embodiments of the present invention can enhance an interface of a flash memory device by increasing the number of operations performed per transmission from a media management system. Further, some embodiments of the invention are designed to interface the flash memory device and media management controller via an interconnection attachment and/or driver common to a second type of data storage device, such as a hard drive.

System and apparatus for increasing the number of operations per transmission for a media management system

A system and apparatus for controlling a burst sequence in a synchronous memory is described. In one embodiment, the system comprises a synchronous memory and a burst read device coupled to the synchronous memory. In one embodiment, the burst read device is configured to sense a page of data as a current page from the synchronous memory, wherein the current page contains a fixed number of words of data. The device is further configured to latch the current page of data, and synchronously read the current page of data, one word at a time. In an alternate embodiment, the burst read device further comprises a wrap-bit. If the wrap-bit is not set, the burst read device is configured to latch the current page of data, adjust a word pointer to indicate a next word of data, and repeat latching and adjusting in a sequential burst read order. If the wrap-bit is set, the burst read device is configured to latch the current page of data, adjust a word pointer to indicate a next word of data, and repeat latching and adjusting in a non-sequential burst read order.

Controlling burst sequence in synchronous memories

A flash EEPROM memory device including a plurality of blocks of flash EEPROM memory cells arranged to be accessed in rows and columns, a query memory storing data defining characteristics of the flash memory device that may be used to initialize software device drivers for accessing the device, and an interface for receiving data and commands addressed to the blocks of flash EEPROM memory cells and generating signals for affecting the purpose of the commands in the flash EEPROM memory device, the interface adapted to receive a command scaled to a range of characteristics of a particular flash EEPROM memory device and respond by returning the data stored in the query memory as output depending on characteristics of the particular flash EEPROM memory device.

Interface for flash EEPROM memory arrays

A method and apparatus for controlling use of an electronic system is described. Use of the electronic system is controlled by programming at least one unique code into an auxiliary memory of the electronic system. The auxiliary memory is a permanently lockable memory that is located outside of a main memory array space. The unique code is compared to at least one component code. Use of the electronic system is controlled based on a predefined relationship between the unique code and the component code.

Method and apparatus for preventing the fraudulent use of a cellular telephone

A method and apparatus for outputting data stored in a non-volatile memory device. The non-volatile memory device includes a non-volatile memory array, an address input for receiving an address indicating a plurality of data values stored in the non-volatile memory array, a sense amplifier circuit to amplify the indicated plurality of data values, a multiplexer to receive the indicated plurality of data values, a clock input for receiving a clock signal and a data selector. The data selector generates a sequence of select signals in response to respective transitions of the clock signal. Each select signal of the sequence of select signals is asserted to the multiplexer to enable the multiplexer to output a respective one of the plurality of data values.

Synchronous page-mode non-volatile memory with burst order circuitry and method thereof

An improved method and apparatus for performing burst read operations in a nonvolatile memory includes a burst read device coupled to the nonvolatile memory, wherein the burst read device senses a page of data from the nonvolatile memory, latches the page of data, synchronously reads the data one word at a time, and senses a next page of data concurrently with the synchronous reading.

Method and apparatus for a nonvolatile memory interface for burst read operations

An apparatus for protecting memory blocks in a block-based flash Erasable Programmable Read Only Memory (EPROM) device is disclosed. A non-volatile memory array includes a number of blocks that are capable of being placed in a locked state or an unlocked state. A volatile lock register and transmits a write protect signal and a volatile lock-down register are coupled to a lockable block in the volatile memory array. A hardware override line is coupled to both the lock register and the lock-down register. The hardware override line temporarily overrides operation of the lock-down register when it transmits a signal at a first logic state. The lock down register may be used to prevent programming of an associated lock register. The lock registers and lock down registers may be embodied in static access memory (SRAM) circuits. A command buffer may be operable to transmit a two cycle command including a first command specifying whether a lock configuration is to be changed and a second command specifying whether a block is to be placed in a lock state, an unlock state, or locked down state. The lock down registers may be capable of being set to lock down only once during a period in which the apparatus is powered up.

Apparatus and method using volatile lock and lock-down registers and for

A method for updating the content of EEPROM memory used for controlling processes run on a microprocessor used to control the operations of a long term memory array which includes moving an update process stored in the EEPROM memory to a random access memory associated with the microprocessor; and then using the update process stored in random access memory for erasing the contents of the EEPROM memory, and furnishing data to the microprocessor on a sector by sector basis from a host computer through an interface used by the microprocessor to provide data to the long term memory array. The data furnished by the host is written sector by sector to the EEPROM memory until the EEPROM memory has been updated.

Method and apparatus for updating flash memory resident firmware through

Synchronous page-mode non-volatile memory with burst order circuitry

A control circuit for a computer component circuit which includes oscillator apparatus for providing square wave pulses at a prescribed frequency, gating apparatus for providing the square wave pulses at an output terminal for use as a clock for the component circuit, timing apparatus for sensing a period during which the component circuit has not performed an operation, and apparatus for disabling the gating apparatus for providing the square wave pulses at an output terminal.

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Diamond Springs, CA, United States of America

Terry L Kendall