Delphi Technologies, Inc.

Delco Electronics Corporation

Terry L Fruehling

Troy L Helm

William D Wise

Dale J Kumke

Kevin M Gertiser

Matthew D Sale

Everett R Lumpkin

Bernard M McFarland

John T Waidner

W James Allen

Roy M Fildes

Mark Thomas Lowden

James M Spall

Charles I Duncan

Bruce C Young

A microcontroller unit (MCU) having a primary, or main, processing unit, a secondary processing unit coupled to the primary processing unit, and a common memory coupled to the primary and secondary processing units is disclosed. A functional compare module is coupled to the primary processing unit and the secondary processing unit for comparing a primary output of the primary processing unit and a secondary output of the secondary processing units to detect a fault if the primary output and the secondary output are not the same. The invention provides a method for detecting a fault in the MCU including the steps of reading a control algorithm stored in the common memory by the primary processing unit, reading the control algorithm stored in the common memory by the secondary processing unit, comparing the primary output and the secondary output and responsively detecting a fault, if the primary output does not match the second output.

Secured microcontroller architecture

An electronic control unit (ECU) includes a central processing unit (CPU), a non-volatile memory bank, a volatile memory bank and a state machine. The state machine is in communication with the CPU and functions to selectively capture information available on an internal bus of the CPU on a cycle-by-cycle basis and store the captured information in the volatile memory, which is also coupled to the CPU.

On-chip instrumentation

A method and circuit for determining the health of a microcontroller is provided having a circuit that includes a bus, a CPU coupled to the bus and a register coupled to the bus. A memory is also coupled to the bus. The memory is utilized by the first CPU. A controller is coupled to the register for controlling reading of the memory. The register generates a signature in response to the memory. The controller compares the reference signature and the second signature. The controller generated a fault signal when the reference signature is unequal to the second signature.

Method and circuit for analysis of the operation of a microcontroller using signature analysis of memory

A method and circuit for determining the health of a microcontroller is a bus having a data line and instruction line. A first CPU is coupled to the bus. A reference memory stores a reference signature. A shift register is coupled to the bus and generates a second signature in response to the data line and instruction line. A controller is coupled to the register and the reference memory for controlling reading of the data line and instruction line. The controller compares the reference signature to the second signature. The controller generates a fault signal when the reference signature is unequal to the second signature.

Method and circuit for analysis of the operation of a microcontroller using signature analysis of data and instructions

A method and circuit for determining the health of a microcontroller is provided having a circuit that includes a bus having data streams thereon. A first CPU is coupled to the bus. A linear feedback shift register is coupled to the bus and generates a signature in response to the data streams. A memory is coupled to the bus. The memory is utilized by the first CPU. A controller is coupled to the register for controlling the reading of the data streams. The register generates a second signature in response to the data stream. The controller compares the reference signature and the second signature. The controller generates a fault signal when the reference signature is unequal to the second signature.

Method and circuit for analysis of the operation of a microcontroller using signature analysis during operation

A system for anti-lock brake and traction control has a controller circuit comprising a microprocessor on a silicon die. Inputs from several variable reluctance wheel speed sensors are multiplexed to a single channel on the same die for signal processing including diagnostics, A/D conversion, square wave generation for each sensor by a state machine, and wheel speed determination from the square waves. The diagnostics include detecting sensor and harness short and open circuits by comparison of signals to programmable thresholds and fault timing and latching by gauging open and short signals against programmable time limits. Common mode noise rejection is accomplished by detecting common mode aberration and disabling an A/D converter during the aberrations. Other diagnostics include inputting known artificial signals at sensor inputs or wheel speed circuit inputs and checking for expected outputs, or by calculating wheel speed in parallel paths having the same square wave inputs and using different algorithms.

Method and apparatus for anti-lock brake single channel wheel speed

A vehicle controller in which inputs from several wheel speed sensors are used to compute wheel speed. A redundant circuit in the controller receives the sensor input signals and computes wheel speed in a different, software intensive, way. The primary and redundantly computed wheel speeds are compared to validate the primary controller circuitry and the portion of the controller used to process compute the redundant speed signal. To additionally verify proper calculation of wheel speed, the system is tested when the vehicle is at rest by applying an artificial sensor signal to the control input and then checking to see whether the controller determined the correct wheel speed.

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Kokomo, IN, United States of America

Terry L Fruehling