International Business Machines Corporation

Terry L Borden

Casper A Scalzi

Michael Gerard Mall

Richard I Baum

Alan G Ganek

Richard J Schmalz

James Lum

Kenneth E Plambeck

Carl Edward Clark

Justin R Butwell

Mark S Farrell

Leslie W Wyman

Roger E Hough

Ronald M Smith

David Joseph Wisneski

Peter H Gum

Donald W McCauley

Julian Thomas

Bharat D Rathi

Francis E Johnson

David Richard Page

John C Rathjen, Jr

John Fenton Scanlon

William K Kelley

George H Bean

Carol E Clark

Iderpal S Narang

Mark E Rakhmilevich

Donald W Mccauley

John C Rathjen

A parallel query processing system comprises a front end processor, a query processing complex attached to the front end processor, and a database on a data repository attached by a first path to the front end processor, and by one or more additional paths to one or more slave processors within the query processing complex. An external operations command processor within the front end processor quiesces database managers in the slave processors to permit maintenance operations by the front end processor, and restarts the slave processors in read-only mode after maintenance operation completion. A splitter/scheduler function in a master processor within the query processor complex receives complex read-only queries from the front end processor, splits them into query elements, schedules the query elements for execution on the slave processors and recombines the execution results to be sent back to the front end processor.

System for parallel processing of complex read-only database queries

A computer system has general purpose registers, control registers and access registers for containing information to allow address space capability. A linkage stack uses protected address space to store state information during program call and program return operations. The linkage stack contains information relating to state entries for the saved information and header and trailer entries to point to other linkage stack sections. A control register contains the pointer to the current linkage stack entry and is changed as the program call or return moves through the stack.

Linkage mechanism for program isolation

A program authorization mechanism for authorizing access to an address space in the main memory of a computer system by a program being run under a multiple address space facility. An access-list entry is associated with each address space, each access-list entry being designated by an access-list-entry token contained in an access register. Each access-list entry includes a private indicator which indicates if the associated address space can be accessed by all programs from this access-list entry or if the associated address space can only be accessed by an authorized program. For program to be authorized, an extended authorization index in a control register must match an access-list extended authorization index in the access-list entry, or the extended authorization index value must be authorized in an authority table associated with the address space. An instruction for testing a given extended authorization index for a given access-list-entry is also disclosed.

Authorization for selective program access to data in multiple address

A method and apparatus is provided to translate the contents of access registers into information for use in performing addressing functions for multiple virtual address spaces. The access registers represent the full addressing capability of the system but do not directly contain the addressing information. The system has a plurality of general purpose registers, a plurality of access registers associated with the general registers, an access list having access list entries which is addressed by the contents of the access register, memory storage for holding address space number second table entries (ASTE), where the contents of the access list entry locate the ASTE and where the ASTE contains the addressing information needed to translate a virtual address when combined with the contents of a general purpose register. Access register translation (ART) consists of the process of determining addressing information by using the access list entry and the ASTE. The results of the ART process are stored in an ART lookaside buffer (ALB) which stores the results of ART while valid for later use.

Multiple address space token designation, protection controls,

The embodiment discloses a method and means for partitioning the resources in a data processing system into a plurality of logical partitions. Host control code may be embodied in programming, microcode, or by special hardware to enable highly efficient operation of a plurality of preferred guest programming systems in the different partitions of the system. The main storage, expanded storage, the channel, and subchannel resources of a system are assigned to the different logical partitions in the system to enable a plurality of preferred guest programming systems to run simultaneously in the different partitions. This invention automatically relocates the absolute addresses of the I/O channel and subchannel resources in the system to their assigned partitions. Also the absolute and virtual addresses of the different guest programming systems are relocated into, as well as page addresses for any expanded storage, their assigned partitions. The guest programming systems generally will be different operating systems. The logical CPU(s) of the guests are dispatched on one or plural real CPUs in the system using the S/370XA SIE (start interpretive execution) instruction. Special operations are provided, including the CPU alerting of other guests in different partitions using I/O interruption signalling. Interception is provided to handle special circumstances.

Logical resource partitioning of a data processing system

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Poughkeepsie, NY, United States of America

Terry L Borden