Motorola Corporation

Terry L Biggs

Donald L Tietjen

Jesse R Wilson

John Michael Hudson

Antonio A Lagana

A memory controller (,) controls accesses to a command-based memory device (,) such as a synchronous DRAM. The memory controller (,) uses an address comparator (,) for both base address matching and command generation. When the memory controller (,) detects an access to the memory device (,) and a control register bit is set, a state machine (,) causes the command to be written to the memory device (,). The memory controller (,) thus allows the memory device (,) to be accessed with little additional circuitry, and to be connected to higher order address bits to speed the access. Since the commands are detected by accesses to the same memory locations as reads and writes, the memory controller (,) avoids creating &ldquo;holes&rdquo; in the memory map.

Memory controller and method for generating commands to a memory

A memory controller (42) supports a mode known as continuous page mode. The memory controller (42) is coupled to a pipelined internal bus and provides control signals to an external bus to control a memory such as a dynamic random access memory (DRAM) (43). The memory controller (42) compares the page portion of a next address to the page portion of the current address. If the addresses match, the memory controller (42) keeps the page open for the next cycle. However if the addresses do not match, or if the next address is not valid at this same point in time during the first access, the memory controller (42) closes the page during the first cycle. The memory controller (42) performs continuous page mode without incurring a penalty when the page is closed.

Memory controller with continuous page mode and method therefor

A data processing system (10) and method is used to recover a CPU from faulty operation. A single timer (38) is used to enable recovery operations. When the timer (38) experiences a first time-out event, a software watchdog interrupt (28) is generated. If the software interrupt (28) is properly handled before another consecutive/subsequent watchdog time out occurs, normal software execution will resume. However, if the software watchdog interrupt is not processed and the watchdog timer (38) experiences a second time-out event while the watchdog time-out interrupt (28) is pending, the timer (38) will generate a bus transfer termination signal (30) and set a status bit (270) within a watchdog status register (44). This assertion of termination signal (30) and the setting of the bit (270) allows the microprocessor to determine that a locked bus state exists. In response to the signal (30) and the bit (270), the locked bus (one or more of busses 22, 24, and/or 26) will attempt to recover from the locked bus state.

System and method for recovering a microprocessor from a locked bus state

A synchronous memory interface feeds back a buffered (34) clock signal to a microcontroller (20) to simplify and improve output hold time for the memory (38). An output delay circuit (36) in the microcontroller (20) is controlled by the same delayed clock signal as the synchronous memory (38). This delay circuit (36) selectively delays memory signals to the synchronous memory (38) from the microcontroller delay circuit (36). The use of flip-flops (40, 44) in the delay circuit (36) provides a mechanism for scan testing. This enables three different selectable modes of operation of the delay circuit (36) providing flexibility in interfacing in different environments.

Synchronous memory interface

A method and apparatus for providing both power and control by way of an integrated circuit terminal (22). In one form, a clock source (12) supplies a periodic signal to a phase lock loop circuit (32) and to a multiplexer (34). The output of the phase lock loop circuit (32) is a second input to the multiplexer (34). The phase lock loop circuit (32) receives its power from a power and control pin (22). The multiplexer (34) receives its power from a power pin (24). The power and control pin (22) is used as a control input to multiplexer (34). Multiplexer (34) uses the power and control pin (22) to select which input to output as a system clock.

Method and apparatus for providing both power and control by way of an

A data processing system (10) having a dual purpose memory (14) comprising multiple cache sets. Each cache set can be individually configured as either a cache set or as a static random access memory (SRAM) bank. Based upon the configuration of the set, the tag store array (58) is used for storage of actual data, in the SRAM mode, or for storage of a set of tag entries in the cache mode. A module configuration register (40) specifies the mode of each set/bank. A set of base address registers (41-44) define the upper bits of a base address of SRAM banks. In SRAM mode, comparison logic (66) compares a tag field of the requested address (50) to the base address to determine an access hit. The least significant bit of the address, tag field is used to select either the tag store array (58) or the line array (60) for the requested address data read or write.

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Austin, TX, United States of America

Terry L Biggs