Mitel Corporation

Terry Kenny

Menno T Spijker

Robert L Van Der Valk

Jerzy Wieczorkiewicz

Krishna Shetty

A digital phase locked loop for recovering a stable clock signal from at least one input signal subject to jitter is disclosed. The loop included a digital input circuit receiving at least one input signal, a digital controlled oscillator for generating an output signal at a desired frequency and a control signal representing the time error in the output signal, a stable local oscillator for providing clock signals to the digital controlled oscillator, and a tapped delay line for receiving the output signal of the digital controlled oscillator. The tapped delay line comprises a plurality of buffers each introducing a delay of less than one clock cycle of the digital controlled oscillator. The tapped delay line produces an output signal from a tap determined by the control signal. A digital phase comparator receives at least one input signal from the input circuit and the output signal from the tapped delay line to generate a digital input signal controlling the digital controlled oscillator.

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Nepean, Canada

Terry Kenny