Texas Instruments Corporation

Stratosphere Solutions, Inc.

Terry James Bordelon, Jr

Amitava Chatterjee

Patrick Robert Smith

Bruce Lynn Pickelsimer

Mahalingam Nandakumar

Brian Edward Hornung

An integrated circuit and method has an isolated well with an improved isolated well contact. The well contact diffusion is isolated from a device diffusion of opposite conductivity type within the isolated well by an isolation transistor gate.

Isolated well contact in semiconductor devices

A method of fabricating a Metal-Oxide Semiconductor (MOS) transistor includes providing a substrate having a substrate surface doped with a second dopant type and a gate stack over the substrate surface, and a masking pattern on the substrate surface which exposes a portion of the substrate surface for ion implantation. A first pocket implantation uses the second dopant type with the masking pattern on the substrate surface. At least one retrograde gate edge diode leakage (GDL) reduction pocket implantation uses the first dopant type with the masking pattern on the substrate surface. The first pocket implant and retrograde GDL reduction pocket implant are annealed. After annealing, the first pocket implant provides first pocket regions and the retrograde GDL reduction pocket implant provides an overlap with the first pocket regions to form a first counterdoped pocket portion within the first pocket regions.

Pocket counterdoping for gate-edge diode leakage reduction

A Metal-Oxide Semiconductor (MOS) transistor includes a substrate having a topside semiconductor surface doped with a first dopant type having a baseline doping level. A well is formed in the semiconductor surface doped with a second doping type. The well forms a well-substrate junction having a well depletion region. A retrograde doped region is below the well-substrate junction doped with the first dopant type having a peak first dopant concentration of between five (5) and one hundred (100) times above the baseline doping level at a location of the peak first dopant concentration, wherein with zero bias across the well-substrate junction at least (&#x3e;) ninety (90) % of a total dose of the retrograde doped region is below the bottom of the well depletion region. A gate structure is on the well. Source and drain regions are on opposing sides of the gate structure.

MOS transistors having reduced leakage well-substrate junctions

An electronic circuit to determine current-voltage characteristics of a plurality of electronic devices under test. The electronic circuit is comprised of a plurality of individual test cells, each of the plurality of test cells is configured to electrically couple to a first terminal of one of the plurality of electronic devices under test and to a first current source. A second terminal of each of the plurality of electronic devices under test couples to a second current source. The circuit employs a current-based measurement method.

Method and apparatus for array-based electrical device characterization

An electronic circuit and method to determine a resistance value of a resistive element. The circuit includes a current source coupled in series with the resistive element. The current source is configured to force a predetermined value of current through the resistive element and includes a transconducting device coupled to the current source. The transconducting device is configured to sense a voltage across the resistive element and transform the voltage into an output current of the transconducting device such that the output current is not dependent upon any other terminal voltages of the transconducting device.

Growing community of inventors

Flower Mound, TX, United States of America

Terry James Bordelon, Jr