Unisys Corporation

Terry J Brunmeier

Larry L Byers

Gary R Robeck

John A Miller

Paul A Laberge

Randy L DeGarmo

A method and apparatus for increasing the efficiency of a dynamic read and/or write operation of a memory element within a computer system. The dynamic read and/or write operation may be performed when the computer system is in a functional mode or a test mode. The present invention may reduce the number of bits that are required to be serially shifted into a design by providing an auto-increment block. It is recognized that most multi-word access to a memory are made to sequential address locations within the memory. The auto-increment block takes advantage of this and automatically manipulates the address thereby not requiring subsequent addresses to be serially shifted into the design. Further, the control word may be stored within the design for subsequent accesses. That is, the support controller may shift a starting address and a control word into the design. The addresses for subsequent accesses may be generated by the auto-increment block, thereby only requiring that the support controller shift a data word to/from the design. This may significantly reduce the time necessary perform the subsequent read and/or write operations.

Method and apparatus for dynamically testing a memory within a computer

A method and apparatus for efficiently reading or writing a number of successive address locations within a memory. In an exemplary embodiment, a processor or the like may not be required to provide an address to a memory unit for each read and/or write operation when successive address locations are accessed. That is, for multiple memory accesses which access successive address locations, the processor or the like may provide an initial address but thereafter may not be required to provide subsequent addresses to the memory unit. The subsequent addresses may be automatically generated by an automatic-increment block.

Method and apparatus for locally generating addressing information for a

A method and apparatus for isolating an error in a system having a controller or the like which access a user via an interface device. The controller or the like may be coupled to the interface device via a first bus and the interface device may be coupled to the user via a second bus. The controller or the like may detect an error in a data transfer from the user to the controller via the interface device, and may isolate the error to the second bus/interface device or the first bus/controller. This up-front error isolation may reduce the amount of analysis required by a service technician after a corresponding PC board or the like is removed from the system, thereby reducing the cost thereof.

Method and apparatus for isolating an error within a computer system

A method and apparatus for efficiently identifying and indicating the severity of the fault within a computer system. In an exemplary embodiment of the present invention, the circuitry of a computer system may be divided into a number of groups. Each group may contain circuitry which may result in the same fault type. For example, predetermined circuitry which, when a fault is detected therein, may have a minimal affect on the normal operation of the computer system may be provided in a first group. Similarly, predetermined circuitry which, when a fault is detected therein, may have an immediate affect on the normal operation of the computer system may be provided in a second group. Each group may provide an error priority signal to a support controller. The support controller may interpret the number of error priority signals provided by the number of groups and may determine the appropriate time to take corrective action thereon.

Method and apparatus for indicating the severity of a fault within a

A method and apparatus for identify the source and nature of an error, without aborting the operation of the computer system. In one embodiment of the present invention, the source of the error may be a hardware element and the nature of the error may be identified as either fatal or non-fatal. If the nature of the error is considered non-fatal, the present invention may correct the error and continue the operation of the computer system. This may allow detected errors to be handled immediately after they occur, rather than aborting the operation of the computer system and waiting for a support controller or the like to analyze the error. This may significantly enhance the reliability and performance of a corresponding computer system. This may be especially important during time critical operations. Further, since the operation of the computer system may be aborted a fewer number of times, the present invention may minimize the amount of data loss. This may be particularly important for high reliability computer applications, including banking applications and airline reservation applications, where the integrity of the data base is of the utmost importance.

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Shoreview, MN, United States of America

Terry J Brunmeier