International Business Machines Corporation

Intel Corporation

Other

Terry I Chappell

Barbara A Chappell

Stanley Everett Schuster

Jerry M Woodall

Mark S Milshtein

Bruce Martin Fleischer

Thomas D Fletcher

Michael P Beakes

Rajiv V Joshi

Sang Hoo Dhong

Wei Hwang

David J Widiger

Rudolf Adriaan Haring

Walter H Henkels

Gary Stephen Ditlow

Kevin Dai

Barry Lee Dorfman

Vinod Narayanan

Milo D Sprague

Mahmut K Ebcioglu

Edward Seewann

Ghavam G Shahidi

Xia Dai

Michael Kevin Ciraula

Robert Alan Philhower

Thao Ngoc Nguyen

Thomas N Jackson

Talal K Jaber

Dieter W Pohl

Martin Emery Beahm

Geroge D Pettit

Kevin (Xia) Dai

George Anthony Halasz

Talal Kamel Jaber

Max Eduardo De Ycaza

Pho Hoang Nguyen

A global clock self-timed circuit initiates a precharge pulse in response to which a domino node is precharged. A self-terminating precharge circuit coupled to the global clock self-timed circuit and the domino node terminates the precharge pulse after the domino node has been precharged.

Global clock self-timed circuit with self-terminating precharge for high frequency applications

A method and a circuit for testing an integrated circuit are disclosed. In one embodiment, a self-resetting dynamic circuit, also known as a fireball circuit, contains a scan circuit and at least one Set Dominant Latches (&ldquo;SDL&rdquo;) where each SDL includes a keeper node. When scan clock is active, the scan data propagates from the scan circuit to the self-resetting dynamic circuit through the keeper node.

Implementation of iscan cell for self-resetting dynamic circuit

A method and apparatus provides an efficient ratioed digital logic structure. The digital logic structure includes ratioed pull-up transistors and pull-down transistors such that the circuit noise margin does not substantially affect gain performance of the ratio stage. In one particular embodiment, a ratioed logic structure includes PMOS transistors and NMOS transistors that receive input voltage signals wherein a current path is induced in the NMOS transistors when a voltage input of zero or less is applied. Another feature of the present invention allows modification of gain performance of the ratio stage by arranging different ratios of the PMOS-to-NMOS transistor channel widths.

Method and apparatus for ratioed logic structure that uses zero or negative threshold voltage

A dynamic incrementer, implemented in the Self Resetting Complementary Metal Oxide Semiconductor (SRCMOS) circuit family, which internally performs single rail calculations and which generates the dual rail result using a strobing technique. The carry-lookahead function is implemented with an OR tree using the complement input signals, resulting in a very fast and economical incrementer.

High performance, low power incrementer for dynamic circuits

A variable width pulse generator. The pulse generator includes a pulse circuit responsive to a reset signal to provide a pulse circuit signal. A variable delay reset loop path, coupled to the pulse circuit, is responsive to the pulse circuit signal to provide the reset signal. A control signal may vary the width of a pulse generated by the circuit by varying the length of a delay associated with the reset loop path. Both a coarse control signal, such as a signal that selectively removes a logic element in the reset loop path, and a fine control signal, such as a signal that controls a tunable delay element in the reset loop path, may be used to adjust the pulse width.

Variable width pulse generator

A computer-based method automatically synthesizes, optimizes and compiles high performance control logic using SRCMOS LOGIC ARRAY MACROS, abbreviated as SLAMs. The method includes a series of steps that transform a high level design description into a set of SLAMs, and includes the steps of partitioning the logic description of a unit into blocks that are suitable for mapping to a target SLAM structure; mapping each logic partition to the target SLAM structure; creating a configuration and relative layout for the internal structure for each SLAM; creating an external description for each SLAM, each description being of sufficient detail to carry out physical design and integration of the unit which contains the SLAM; assembling the partitions implemented as SLAMs with other macros in the unit; resolving interface conflicts between the different macros by selecting appropriate signal interfaces for various SLAMs; repeatedly changing the external specifications of the various SLAMs; analyzing the performance of the unit; automatically compiling the schematic and layout of each SLAM within the unit based on the configuration and relative layout; and assembling the macros and analyzing the design for design rule violations.

Method and apparatus for synthesizing and optimizing control logic based

An embodiment of the present invention includes a switchable conductive pathway between a number of intermediate nodes in a domino stage, up to and including every intermediate node, and a voltage source. In operation, this circuit configuration prevents the problems associated with charge sharing. The voltage, at the voltage source which is coupled to the intermediate nodes, is substantially equal to the voltage at a voltage source that is coupled by way of a domino precharge circuit to the output node of the domino stage. The switchable conductive pathways are switched on at the start of the precharge phase, and switched off at the beginning of the evaluation phase. In this way, intermediate node voltages in a domino stage are actively maintained, even after the main precharge control signal has been deasserted. Active maintenance of the intermediate nodes is suspended during the evaluation phase. In a further aspect of the present invention, the switchable conductive pathways in the domino stages of a first domino chain are controlled by signals that are generated by a second domino chain that is parallel to the first domino chain.

Charge sharing protection for domino circuits

A pulse generating circuit includes a first pulse generating circuit for generating a first output pulse, and a second pulse generating circuit for outputting a second output pulse. Each pulse generating circuit comprises a stack of two n-channel transistors and a reset circuit. The reset circuit includes two p-channel transistors and two inverters and is provided for automatically resetting the pulse generating circuits. The second pulse generating circuit includes a delay element for introducing an additional gate delay in the generation of the second output pulse. The additional gate delay introduces an asymmetry in the output pulses which offsets or cancels a previously introduced asymmetry of an input clock signal to generate an output clock signal having a constant period. Clock gating circuitry is provided for selectively enabling and disabling at least one of said pulse generator circuits.

High gain pulse generator circuit with clock gating

A logic circuit family implements self-resetting CMOS logic array macros (SLAMs) which include a plurality of inputs to which a plurality of data input signals can be applied; a plurality of input buffers coupled to receive the input signals from the inputs; a NOR circuit coupled to receive the outputs of the input buffers and a pulsed logic timing signal synchronized within a predefined window with the arrival of the data input signals; an output buffer coupled to receive the output of the NOR circuit; and an output at which a data output signal is produced, with the output signal being a logical NOR of the data input signals; and with each of the NOR circuit, the plurality of input buffers, and the output buffer optionally having a separate reset input to reset it to a standby state. The SLAMs address the very high pressure on the performance of both control logic and control logic design systems. The distinguishing features of SLAMs are uniquely combined to allow the automated design, from a logic description and interface specifications, of a complete macro satisfying predetermined design guidelines.

Compiled self-resetting CMOS logic array macros

A low-power pulse-to-static conversion latch circuit is disclosed. The circuit includes self-timed control and an n-bit latch array both designed utilizing self-resetting CMOS circuit techniques. The self-timed feature of the control requires only one system clock input. The evaluation, reset and write-enable controls are all generated within a control macro. The latch is level sensitive scan design (LSSD) compatible and complies with self-resetting CMOS (SCRMOS) test modes. Use of these latches facilitates the synchronization, pipelined operation, power-management, and testing of advanced digital systems employing a mix of static and dynamic circuits to achieve high performance.

Pulse-to-static conversion latch with a self-timed control circuit

A logic structure adapted to receive pulsed active input signals produces a logical output with a very small inherent switching delay. Pull-down transistors and complementary pull-up transistors are ratioed such that the default logical output level remains close to nominal even when the logic structure sinks or sources a DC current. When the pulsed input signals are inactive, no DC current path is enabled.

High speed ratioed CMOS logic structures for a pulsed input environment

A high performance register that can be used as a pipelined register in logic chips that are designed using a pulsed logic methodology is described. The register features minimal setup time, pulse catching and pulse launching. The register circuitry complies with and implements a circuit-level test methodology for pulsed logic that features the ability to inhibit the reset of pulses, to force resets and to operate the circuits in a pseudo static mode. The register also complies with the level sensitive scan design (LSSD) methodology. Also described is a state-holding static master-slave register that complies with a pulsed logic design methodology, the register exhibiting an automatic power reduction feature and a simplified modular register bit design which can easily be adapted to either static domino or pulsed logic. The register is also LSSD compliant. Also described is the means and method for allowing static transmission gate input registers to comply with the static evaluate test mode. The automatic power reduction feature can be extended to downstream logic.

High performance registers for pulsed logic

The invention provides a technique, given a netlist containing a description of the terminal connections and the length and width of each device in a circuit, for automatically producing a layout for each device in that circuit.

Parameterized cells for generating dense layouts of VLSI circuits

A pulsed logic circuit test methodology and circuitry therefor are disclosed. The methodology and circuitry allow the inhibiting of reset pulses, the ability to force resets and the ability to test the circuit in a pseudo-static mode of operation.

Methodology to test pulsed logic circuits in pseudo-static mode

A parallel self-resetting parallel binary adder provides high speed addition and subtraction. The adder combines the advantages of a fully custom design methodology with the higher performance potential of self-resetting complementary metal oxide semiconductor (CMOS) circuits. The adder logic architecture is carry look-ahead with two bit groups and requires six rows of merge logic to calculate the carry out of the Most Significant Bit (MSB). Loading on the critical path of the adder is reduced by moving as many merge blocks as possible to later rows. This allows the fan-out per stage in the critical path to be reduced from around three to two or less. The adder utilizes a bubble pipelined circuit architecture. For the adder, a bubble pipe segment consists of a row of self-resetting circuit blocks. A fast cycle time and minimum delay for each block is achieved by using fast forward amplification of the leading edge of the pulsed input signals followed by quick self-resetting of all nodes back to their standby state.

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Portland, OR, United States of America

Terry I Chappell