Ford Motor Company Limited

Terry Eugene Downs

William Eugene Gioiosa, Jr

Scott Martin Kerstein

Burst memory transfer from a memory to a microprocessor (CPU) is accomplished using analysis including determining first and second conditions. If an output enable is consecutively activated for more than one consecutive system clock cycle, following the address phase, the memory will initiate a burst transfer sequence. The addresses of subsequent data bytes or words following the first byte or word are determined by the memory advancing or incrementing its internal address counter until the burst transfer has been suspended or terminated. If the output enable pin is deactivated prior to the next address phase requested by the CPU, burst transfer will be suspended until the output enable pin is activated again. If the CPU requests the next address phase (chip enable activated) from the memory while the output enable is activated, the burst in progress will be terminated.

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North Wales, PA, United States of America

Terry Eugene Downs