Nortel Networks Corporation

Northern Telecom Limited

Terry E Newell

Brian Neil Baker

Ruth Beyerlein

Anthony K Brown

John M Williamson

Brian N Baker

Bing L Wong

Robert Zani

Alexandre J Guterman

A high availability computing system having multiple processing elements capable of simultaneous execution of multiple software programs and seamless software upgrades is disclosed. The system comprises multiple processing elements, each processing element capable of accessing memory at processing element memory addresses; and multiple memory modules each having a plurality of alterable memory units, each memory unit identified by a system memory address within a defined address space. The system further includes a memory element interface in communication with each of the memory elements permitting alteration of the defined address space for the memory element. An address mapper is interconnected between each of the processing elements and at least one of the memory elements. The address mapper is capable of mapping a processing element memory address to a global memory address within a defined address space. Thus, the system may allocate memory addresses used by a single one of the memory elements to an address space used by only a single processing element. The system further has access ports to each of the memory elements, thus allowing the single processing element limited access to other memory modules. Conversely, other processing elements may have limited access to the single memory module. As a result, the single computing system may be divided into two logical computing systems. Software upgrades may be loaded into one system, without interrupting the other system.

High availability computing system

A method and apparatus for receiving status information from shared logical memory modules in a computer system including redundant memory. The status information includes whether the shared logical memory modules are in a transitional state and the number of logical memory modules in the mirror set. When shared logical memory modules are added or removed from redundant memory they go through a transitional state when the memory card may respond to a request for data held on the card, but that data may be unreliable. Checking this status information allows better error checking of data and fault detection of the shared logical memory module.

High availability asynchronous computer system

A bus for high signal quality interconnections, comprising means for producing at least one common mode reflection, often for differential transmission line interconnections. Also, a bus for high signal quality interconnections further comprising means for under-damping the signal and/or reducing the common mode noise. In both cases the means are at least one impedance termination. To produce common mode reflections, there are non-contact couplers terminated by short and open circuits, which cause the reflections from via connectors and other like impedance discontinuities to be re-reflected in common mode so that they are rejected by a differential receiver. To produce under-damping of the signal and/or a reduction of the common mode noise, capacitive terminations are used. The under-damping of the signal sharpens in the falling edge of the coupler pulses.

Noise cancellation modification to non-contact bus

The invention provides a mechanism for allowing a share memory/parallel processing architecture to be used in place of a conventional uni-processing architecture without requiring code originally written for the conventional system to be rewritten. Exclusive Access and Shared Read Access implementations are provided. A rollback mechanism is provided which allows all the effects of a task to be undone.

Growing community of inventors

Kanata, Canada

Terry E Newell