Cray Incorporated

Cray Research, Inc.

Terry D Greyzck

Peter M Klausler

William F Long

David W Oehmke

William R Fulton

Gary W Elsesser

Matthew F Taylor

A system implementing a method for generating code for execution based on a SIMT model with parallel units of threads is provided. The system identifies a loop within a program that includes vector processing. The system generates instructions for a thread that include an instruction to set a predicate based on whether the thread of a parallel unit corresponds to a vector element. The system also generates instructions to perform the vector processing via scalar operations predicated on the predicate. As a result, the system generates instructions to perform the vector processing but to avoid branch divergence within the parallel unit of threads that would be needed to check whether a thread corresponds to a vector element.

Mapping vector representations onto a predicated scalar multi-threaded system

A system and method of compiling program code, wherein the program code includes an operation on an array of data elements stored in memory of a computer system. The program code is scanned for an equation which operates on data of lengths other than the limited number of vector supported data lengths. The equation is then replaced with vectorized machine executable code, wherein the machine executable code comprises a nested loop and wherein the nested loop comprises an exterior loop and a virtual interior loop. The exterior loop decomposes the equation into a plurality of loops of length N, wherein N is an integer greater than one. The virtual interior loop executes vector operations corresponding to the N length loop to form a result vector of length N, wherein the virtual interior loop includes one or more vector atomic memory operation (AMO) instructions, used to resolve false conflicts.

Using vector atomic memory operation to handle data of different lengths

A system and method of compiling program code, wherein the program code includes an operation on an array of data elements stored in memory of a computer system. The program code is scanned for operations that are vectorizable. The vectorizable operations are examined to determine whether they should be executed at least in part in a vector atomic memory operation (AMO) functional unit attached to memory. If so, the compiled code includes vector AMO instructions.

System and method for managing processor-in-memory (PIM) operations

A system and method of compiling program code, wherein the program code includes an operation on an array of data elements stored in memory of a computer system. The program code is scanned for an equation which may have recurring data points. The equation is then replaced with vectorized machine executable code, wherein the machine executable code comprises a nested loop and wherein the nested loop comprises an exterior loop and a virtual interior loop. The exterior loop decomposes the equation into a plurality of loops of length N, wherein N is an integer greater than one. The virtual interior loop executes vector operations corresponding to the N length loop to form a result vector resident in memory, wherein the virtual interior loop includes a vector atomic memory operation (AMO) instruction.

Vector atomic memory operation vector update system and method

A computer system is operable to identify index elements in a vector index array that cannot be processed in parallel by calculating a complement modified bit matrix compare function between a first matrix filled with elements from the vector index array and a second matrix filled with the same elements from the vector index array.

Inclusive 'OR' bit matrix compare resolution of vector update conflict masks

The precise detection of errors in computer programs using the hardware watchpoint mechanism found in computers is disclosed. In one embodiment, a software detection phase of a method detects the approximate location of an error, generating information regarding this approximate location. In this embodiment, a hardware watchpoint phase of the method detects the precise location of the error based on the information generated by the software detection phase, generating information regarding the precise location. Finally, in this embodiment of the invention, a debugger phase of the method identifies the statement in the computer program causing the error, based on the information generated by the hardware watchpoint phase.

Precise detection of errors using hardware watchpoint mechanism

An optimization method to be carried out within a digital computer under programmed control for eliminating or removing from a loop body alternate exit tests substantially of the form .alpha.i+.beta.cond.phi., where .alpha., .beta. and .phi. are loop invariant expressions, i is the innermost loop index variable, and cond is one of the relational operators (=,.noteq.,&gt;,.gtoreq.,&lt;,.ltoreq.). Each alternate exit test is compared to a list of elimination conditions. If an alternate exit test matches one of the elimination conditions, it is eliminated entirely from the loop body. If the alternate exit test cannot be eliminated, it is then compared to a list of restriction conditions. If the alternate exit test matches one of the restriction conditions, the loop index upper bound is modified if necessary and the alternate exit test is moved from inside to outside of the loop body. The resulting altered loop body is near optimum in terms of both the storage area utilized and the program execution time.

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Eagan, MN, United States of America

Terry D Greyzck