International Business Machines Corporation

Terry Cain Coughlin, Jr

Douglas Willard Stout

Joseph Maryan Milewski

Anthony Correale, Jr

Loc Khac Nguyen

Steven Frederick Oakland

William Frederick Lawson

Roger Paul Gregor

David Jia Chen

Gregg R Castellucci

Geoffrey Wang

Akio Miyoshi

David W Stout

William Fredrick Lawson

A method, apparatus and computer program product are provided for implementing application specific integrated circuit (ASIC) designs having high performance and reduced leakage current. Standard voltage threshold (SVT) circuits in a SVT circuit library are identified. For each SVT circuit, each SVT PFET is replaced with a low voltage threshold (LVT) PFET to provide a hybrid alternate voltage threshold (AVT) circuit. Then the AVT circuits are saved in an alternate voltage threshold circuit library. The AVT circuit library provides enhanced performance as compared to the SVT circuit library without the high leakage current resulting from a LVT circuit library.

Method, circuit library and computer program product for implementing enhanced performance and reduced leakage current for ASIC designs

A decoupling capacitor includes a fixed resistance in series with the capacitor, the resistance formed by contacts connecting a polysilicon layer to metal and a diffusion layer to metal; the contacts being of location and quantity sufficient for limiting defect current while allowing the capacitor to function at high frequency. N pairs of contacts in at least two sets of contacts are separated by a distance K sufficient to achieve a leakage limiting resistance of R and a bandwidth limiting resistance of R/2.

Controlled leakage CMOS decoupling capacitor for application specific integrated circuit libraries

A method of, and a circuit for, impedance control. The method comprises the steps of providing an input/output cell having a controllable input/output impedance, providing a reference cell including a node having a variable voltage, and comparing the voltage of the node to a reference voltage. The voltage of the node is adjusted during a defined period and according to a defined procedure, and during that defined period, a digital signal is generated. That digital signal is transmitted to the input/output cell to adjust the input/output impedance. Preferably, the circuit is embodied as a digital controller designed as a synthesized core or macro. The advantage of this implementation is that it never has to be redesigned in future technologies. The digital controller may be carried over to future technologies in the form of VHDL code, which is pure logic and independent of technology.

ASIC architecture for active-compensation of a programmable impedance I/O

The protection circuit of the present invention addresses the problem of indeterminate logic levels caused by loss of one of the power supplies in a two-power-supply CMOS integrated circuit. The circuit of the present invention replaces the typical scheme of power supply sequencing to fix the problem. The circuit disclosed herein detects the state of the core voltage and disables the output drivers when the core voltage is detected as being off. The disabled drivers are put into a high impedance state, thereby eliminating the potential for damage and eliminating the need for power supply sequencing. The invention also protects against the sudden loss of the integrated circuit core voltage, VDD, power supply during normal operation.

Dual rail power supply sequence tolerant off-chip driver

A high voltage tolerant CMOS input/output interface circuit. In this circuit, a process feature called &ldquo;dual-gate&rdquo; or &ldquo;thick-oxide&rdquo; process is used on any devices that will be exposed to high voltage. The thick-oxide devices have a larger capacitance and lower bandwidth, and therefore, preferably, they are only used where exposure to high voltage can cause damage. The remaining devices on the interface circuit may all use a standard process with the thinner oxide, allowing the I/O and the core IC to run at maximum speed. The circuit design topology also limits the number of devices that are exposed to high voltage. Preferably, the protection scheme is broken down into two parts: the driver and receiver.

Using thick-oxide CMOS devices to interface high voltage integrated circuits

A state saving circuit and method for using the same. The circuit comprises a first latch powered by an uninterrupted power supply, wherein the first latch includes a first pair of cross coupled inverters for storing data, and includes an input cut-off control for isolating the data in the first pair of cross coupled inverters; a second latch coupled to an output of the first latch and powered by an interruptible power supply, wherein the second latch includes a second pair of cross coupled inverters and a clock input for latching the data from the first latch to the second latch; and wherein an interruption of power to the second latch results in a state being saved in the first latch.

CMOS state saving latch

Receiver circuit providing interface between a legacy system sourcing logic signals including high logic level signals at first voltage levels to semiconductor IC devices operating at second voltage levels, wherein the first voltage levels are greater than the second voltage levels. The receiver circuit comprises: a pass gate device receiving the input voltages including high level logic signals at first logic levels and translating the high logic level signals to an intermediate voltage level for output at a first circuit node, the intermediate voltage level being less than the first voltage level; a first inverter device for receiving the translated voltages at the intermediate voltage levels and inverting the voltages for output at a second circuit node, whereby high input logic level voltages are pulled down at the second node and low input logic level voltages are pulled up at the second node; a circuit element in series with the first inverter device for connecting the first inverter device to a voltage supply source that provides pulled up signals at the second voltage levels in response to low logic level input voltages; and, a circuit responsive to pulled down voltage at the second node for deactivating the first circuit element to thereby prevent leakage current to ground through the first inverter device. Stable switching of voltages is achieved at the second node in a manner that eliminates leakage current between the voltage supply source providing pulled up signals at the second voltage levels and the receiver input.

5V-tolerant receiver for low voltage CMOS technologies

A high voltage tolerant receiver that matches a voltage drop across an NFET pass-gate at the input to the receiver with a voltage drop across a semiconductor device, formatted as a diode, and connected between an input stage and an input stage voltage supply source.

High voltage tolerant receivers

Two-supply protection circuit

A low power CMOS bidirectional I/O buffer that translates low voltage core logic level signals into the higher voltage logic level signals. A first predrive stage is provided, comprising buffers (e.g., CMOS inverters) for tuning and balancing the circuit and the core signal combining circuit of a second predrive stage, thereby enabling IC designers to reduce the size of transistors in the level-shifting stage and providing more flexibility in the tuning of the predrive circuitry to synchronize or balance the logical transitions of the complementary transistors of the output driving stage. The invention provides a faster balanced level-shifting output buffer which enables higher frequency operation.

Level shifting CMOS I/O buffer

A latched receiver circuit capable of receiving data and clock simultaneously. New data is latched at every clock cycle without delay or buffering of the data or the clock. The latched receiver may also receive and latch small signals without the aid of a receiver preamp or added delay.

Zero set-up high speed CMOS latched-receiver

A signal detector circuit in a data receiver including a programmable hysteresis circuit for setting and detecting the presence of both a threshold minimum data signal level and a reset signal level higher than the minimum signal level.

Growing community of inventors

Endicott, NY, United States of America

Terry Cain Coughlin, Jr