International Business Machines Corporation

Globalfoundries Inc.

Stmicroelectronics Gmbh

Tokyo Electron Limited

Infineon Technologies Ag

Advanced Micro Devices Corporation

Other

Globalfoundries U.S. Inc.

Elpis Technologies Inc.

Terry Allen Spooner

Lawrence Alfred Clevenger

Chih-Chao Yang

Shom Ponoth

Shyng-Tsong Chen

Baozhen Li

Kirk David Peterson

Wei Wang

Junli Wang

Daniel C Edelstein

Roger Allan Quon

Sampath Purushothaman

Qinghuang Lin

Hsueh-Chung Chen

Hosadurga K Shobha

Theodorus E Standaert

Elbert Emin Huang

Yann Mignot

Griselda Bonilla

Satyanarayana Venkata Nitta

Muthumanickam Sankarapandian

Ravi Prakash Srivastava

David V Horak

Michael Rizzolo

Takeshi Nogami

Benjamin David Briggs

John Edward Sheets, Ii

Stephen McConnell Gates

Koichi Motoyama

John Anthony Fitzsimmons

John Christopher Arnold

Stephen Edward Greco

Carl John Radens

John H Zhang

Lars W Liebmann

Alfred Grill

Timothy Joseph Dalton

Christian Lavoie

Andrew Herbert Simon

Nicole A Saulnier

Kaushik Arun Kumar

Yiheng Xu

Joe Lee

Douglas M Trickett

Yannick Feurprier

Clement Hsingjen Wann

Robert Dennis Miller

Oscar Van Der Straten

Chi-Chun Liu

Eric Andrew Joseph

Yun-Yu Wang

Erdem Kaltalioglu

Willi Volksen

Yongan Xu

Cheng Chi

Nicholas V Licausi

William J Cote

Sunfei Fang

Douglas C La Tulipe, Jr

Jason Eugene Stephens

Michael Wayne Lane

Gregory M Fritz

Christy Sensenich Tyberg

Robert Rosenberg

Wenhui Wang

Somnath Ghosh

Mark Hoinkis

Satya Venkata Nitta

Matthew S Angyal

Habib Hichri

Geraud J Dubois

Akil Khamisi Sutton

Richard Stephen Wise

Prasad Bhosale

Craig Child

Andrew P Cowley

Stefanie Ruth Chiras

Jia Lee

Glenn A Biery

Yun Yu Wang

Son Van Nguyen

Cyril Cabral, Jr

Christopher J Penny

Sanjay C Mehta

Richard Stephan Wise

Jinping Liu

Christos Dimitrios Dimitrakopoulos

Jiehui Shu

Ashim Dutta

David Lee Rath

Kwong Hon Wong

Kaushik Chanda

James John Kelly

Darryl D Restaino

Louis DeWolf Lanzerotti

Kelly Malone

Patrick William Dehaven

Atsushi Ogino

Wei-Tsu Tseng

Chester T Dziobkowski

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure is provided, the memory area interconnect structure comprising metal interconnects formed in dielectric material. A dielectric cap layer is formed on exposed surfaces of the memory area and the non-memory area. A bottom metal contact is formed on a first metal interconnect of the memory area interconnect structure, the bottom metal contact in a trench in the dielectric cap layer. A memory element stack pillar is formed on the bottom metal contact. A dielectric layer is formed on exposed surfaces of the memory area and the non-memory area utilizing a non-conformal deposition process. The dielectric layer is removed from sidewalls of the memory element stack pillar.

Magnetoresistive random-access memory (MRAM) with preserved underlying dielectric layer

Metal interconnect structures are reworked to address possible voids or other defects. Etching of initially deposited interconnect metal to open voids is followed by reflow to accumulate interconnect metal at the bottoms of trenches. Additional interconnect metal is deposited over the initially deposited interconnect metal by electroplating and/or electroless plating. Additional diffusion barrier material may be deposited and patterned prior to deposition of the additional interconnect material.

Rework for metal interconnects using etch and thermal anneal

A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device, and selectively forming a contact region on the contact stud. The selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud. An interlevel dielectric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region.

Contacts having a geometry to reduce resistance

Back end of line metallization structures and methods for fabricating self-aligned vias. The structures generally include a first interconnect structure disposed above a substrate. The first interconnect structure includes a metal line formed in a first interlayer dielectric. A second interconnect structure overlies the first interconnect structure. The second interconnect structure includes a second cap layer on the first interlayer dielectric, a second interlayer dielectric thereon, and at least one self-aligned via in the second interlayer dielectric conductively coupled to at least a portion of the metal line of the first interconnect structure, wherein any misalignment of the at least one self-aligned via results in the at least one self-aligned via landing on both the metal line of the first interconnect structure and the second cap layer. The second cap layer is an insulating material.

Interconnect structures including self aligned vias

Methods of self-aligned multiple patterning. A hardmask is deposited over an interlayer dielectric layer. A mandrel is formed over the hardmask. A block mask is formed that covers a first lengthwise section of the mandrel and that exposes second and third lengthwise sections of the mandrel. After forming the block mask, the second and third lengthwise sections of the mandrel are removed to define a pattern including respective first and second mandrel lines that are separated from each other by the first lengthwise section of the mandrel. The first mandrel line and the second mandrel line expose respective portions of the hardmask, and the first lengthwise section of the mandrel line covers another portion of the hardmask. The pattern is transferred to the hardmask with an etching process, and subsequently transferred to the interlayer dielectric layer with another etching process.

Multiple patterning with mandrel cuts defined by block masks

The present disclosure relates to a structure which includes a first metal layer patterned as a mandrel, a dielectric spacer on the first metal layer, and a second metal layer on the dielectric spacer.

Metal on metal multiple patterning

A method is presented for forming self-aligned vias by employing a top level line pattern. The method includes forming first conductive lines within a first dielectric material, recessing one conductive line of the conductive lines to define a first opening, filling the first opening with a second dielectric material, and forming a sacrificial block perpendicular to and in direct contact with a non-recessed first conductive line. The method further includes forming a single via directly underneath the sacrificial block by recessing the non-recessed first conductive line, removing the sacrificial block to define a second opening, and filling the second opening with a conductive material to define a second conductive line such that the single via aligns to both the non-recessed first conductive line and the second conductive line.

Interconnect integration scheme with fully self-aligned vias

A method is presented for forming self-aligned vias by employing top level line double patterns. The method includes forming a plurality of first conductive lines within a first dielectric material, recessing one or more of the plurality of first conductive lines to define first openings, filling the first openings with a second dielectric material, and forming sacrificial blocks perpendicular to the plurality of first conductive lines. The method further includes forming vias directly underneath the sacrificial blocks, removing the sacrificial blocks, and constructing a plurality of second conductive lines such that the vias align to both the plurality of first conductive lines and the plurality of second conductive lines.

Double patterning interconnect integration scheme with SAV

A semiconductor device and method of making the same, wherein in accordance with an embodiment of the present invention, the device includes a first conductive line including a first conductive material, and a second conductive line including a second conductive material. A via connects the first conductive line to the second conductive line, wherein the via includes conductive via material, wherein the via material top surface is coated with a liner material, wherein the via is a bottomless via.

Semiconductor via structure with lower electrical resistance

A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.

Self aligned via and pillar cut for at least a self aligned double pitch

According to an embodiment of the present invention, a method for forming contacts includes forming an oxide layer over and along a first liner layer. A first spacer layer is formed along the first liner layer opposing the oxide layer. A work function metal layer is formed along the first spacer layer opposing the first liner layer. A gate is formed on and along the work function metal opposing the first spacer. A second spacer layer is formed on the oxide layer. Portions of the oxide layer, the first liner layer, the first spacer, the work function metal layer and the second spacer layer are removed which forms a recess between the gate and the first spacer layer. A second liner layer is deposited in the recess. A low-resistance metal is deposited in the removed portions to form the first contact.

Low resistance contact for transistors

Back end of line (BEOL) structures and methods generally includes forming at least two adjacent conductors separated by a space formed in a first dielectric material, wherein a liner layer is intermediate the first dielectric material and each of the at least two adjacent conductors. A second dielectric material in the space between the at least two adjacent conductors and in contact with the first dielectric material at a bottom surface thereof, wherein the first dielectric material is different from the second dielectric material, and wherein the first dielectric material has a nitrogen enriched surface at an interface between the first dielectric material and the second dielectric material. The nitrogen enriched surface can be formed by plasma nitridation, thermal nitridation, or laser annealing in the presence of nitrogen gas, ammonia, or a combination thereof.

Surface modified dielectric refill structure

Growing community of inventors

Clifton Park, NY, United States of America

Terry Allen Spooner