Advanced Micro Devices Corporation

Terri A Couteau

Anthony John Toprac

Laura Pressley

Michael J Satterfield

Richard J Markle

William Jarrett Campbell

W Jarrett Campbell

Bryon K Hance

David Hendrix

Daniel E Sutton

Deborah J Riley

Stacie Y Brown

The present invention is generally directed to various methods of controlling wet chemical processes in forming metal silicide regions, and a system for performing same. In one illustrative embodiment, the method comprises providing a substrate having a layer of unreacted refractory metal and at least one metal silicide region formed thereabove, performing a wet chemical process to remove at least a portion of the layer of unreacted refractory metal, measuring at least one characteristic of the portion of the layer of unreacted refractory metal while the wet chemical process is being performed, and controlling at least one parameter of the wet chemical process based upon the measured at least one characteristic of the portion of the layer of unreacted refractory metal. In another illustrative embodiment, the method comprises providing a substrate having a layer of unreacted refractory metal and at least one metal silicide region formed thereabove, performing a wet chemical process to remove at least a portion of the layer of unreacted refractory metal, measuring at least one characteristic of the portion of the layer of unreacted refractory metal after at least some of the wet chemical process has been performed, and controlling at least one parameter of the wet chemical process based upon the measured at least one characteristic of the portion of the layer of unreacted refractory metal.

Methods of controlling wet chemical processes in forming metal silicide regions, and system for performing same

Various methods of inspecting circuit structures are provided. In one aspect, a method of detecting structural defects in a circuit structure is provided. A natural frequency of the circuit structure is determined and the circuit structure is immersed in a liquid. A first plurality of sonic pulses is sent through the liquid. The first plurality of sonic pulses have a first frequency range selected to produce a plurality of collapsing bubbles proximate the circuit structure. The collapsing bubbles produce a second plurality of sonic pulses that have a second frequency range near or including the natural frequency of the circuit structure whereby the second plurality of sonic pulses causes the circuit structure to resonate. Thereafter, the circuit structure is inspected for structural damage. Early identification of crystalline defects is facilitated.

Method of detecting crystalline defects using sound waves

Various methods and apparatus are provided for testing an ion implantation tool. In one aspect, a method of testing an ion implanter is provided that includes forming a mask with a preselected pattern on a substrate. An ion implant is performed on the mask with the ion implanter. Following the ion implant, a scan of the mask is performed to identify any defects thereon. Defects appearing on the mask following the implant are indicative of latent mechanisms at work within the implanter. Ion implanter induced defects may be economically analyzed.

Method and apparatus for detecting ion implant induced defects

Methods of patterning sidewall spacers are provided. In one aspect, a method of fabricating a circuit device includes forming a gate on a substrate and forming a first oxide spacer and a second oxide spacer adjacent to the gate. The width of the gate and the first and second oxide spacers is measured. The widths of the first and second oxide spacers are trimmed if the width of the gate and the first and second oxide spacers exceeds a preselected maximum value by exposing the first and second oxide spacers to a solution of ammonium hydroxide, hydrogen peroxide and water for a preselected like and rinsing with deionized water. Spacer width may be finely tuned to reduce the risk of weak overlap and to improve device characteristics through shorter channels.

Control of transistor performance through adjustment of spacer oxide profile with a wet etch

The present invention is directed to a method of controlling the width of a gate electrode based upon the etch rate of a chemical bath. In one illustrative embodiment, the method comprises determining an etching rate for a chemical bath, determining the manufactured width of the gate electrode, and varying the time duration of an etching process performed in the bath depending upon the etch rate of the bath and the width of the gate electrode.

Method of controlling feature dimensions based upon etch chemistry concentrations

A method for processing a semiconductor topography is presented. In the present processing method, a semiconductor topography may be provided having a polysilicon feature arranged above a semiconductor substrate. The polysilicon feature may have an initial polysilicon feature critical dimension (CD). A chemical mixture, preferably contained in a chemical vessel, may also be provided. A polysilicon etch rate-effective attribute of the chemical mixture may be measured. Subsequently, an exposure time to the chemical mixture for the semiconductor topography may be calculated from the polysilicon etch rate-effective attribute, the initial polysilicon feature CD, and a goal polysilicon feature CD. By calculating an exposure time for the semiconductor topography in such a manner, the method preferably allows a final polysilicon feature CD to be more accurately controlled than in conventional processes.

System and method for controlling polysilicon feature critical dimension during processing

A method of performing a nitride strip process step for a plurality of semiconductor wafers includes partially draining the chemical solution within a chemical bath after every nitride strip in which the oxide etch rate is within a specified range. If the oxide etch rate is above the specified range, the partial drain is performed. Once the etch rate falls within the range, the partial drain is performed every time a bath increment signal is received. If the etch rate falls below the specified range, then the bath is completely drained so that the solution may be replaced with fresh chemicals. While it is generally desirable to minimize the amount of field oxide that is removed during the nitride strip process step, the field oxide etch should be maintained at a specified level because, when below that level, the chemical solution silicon content is too high risking the possibility that the silicon will precipitate and cause undesirable effects including coating the wafers being stripped of nitride. The partial drain time is adjusted from a nominal rate according to measured oxide etch rates. For a first bath in a sequential series of baths, the nominal partial drain time is fifteen seconds. For a second bath in the sequential series of baths, the nominal rate is ten seconds.

Growing community of inventors

Rosanky, TX, United States of America

Terri A Couteau