Acer Inc.

National Yang Ming Chiao Tung University

Realtek Semiconductor Inc.

National Applied Research Laboratories

Terng-Yin Hsu

Wei-Chi Lai

Tsung-Yu Tsai

You-Hsien Lin

Hsuan-Li Lin

Shau-Yu Cheng

Chi-Hsu Chen

Jung-Chin Lai

Hsiang-Ming Yen

Ying-Liang Chen

Yuan-Te Liao

Kai-Shu Su

Cheng-Yuan Lee

A method and apparatus for measuring an elapsed time from a starting signal to an ending signal in a time-to-digital converter. Primarily, the invention calculates an amount of complete cycles from the starting signal to a starting edge of a next clock cycle or the next Nth clock cycle (N is a natural number great than one) after the clock cycle corresponding to the ending signal. The amount is multiplied by a cycle time of the coarse clock to obtain a coarse time value. A time residue is calculated from the ending signal to the starting edge. Finally, the time residue is subtracted from the coarse time value to obtain a required time.

Time-to-digital converter using time residue feedback and related method

Methods of data allocation and signal receiving, a wireless transmitting apparatus, and a wireless receiving apparatus are provided based on orthogonal frequency division multiplexing (OFDM) technology. The wireless transmitting apparatus obtains a data stream and allocates the data stream to a first sub-carrier set. Each of the first sub-carrier set and a second sub-carrier set has sub-carriers with opposite frequencies to each other, respectively. The second sub-carrier is emptied or allocated according the data stream allocated to the first sub-carrier set. The data stream is converted into an OFDM signal transmitted through a transmitting module. The wireless receiving apparatus includes a single branch receiver for receiving a radio frequency (RF) signal and outputting a baseband signal. Subsequently, the data stream is restored from the baseband signal.

Methods of data allocation in subcarriers and related apparatuses using the same

Methods of data allocation and signal receiving, wireless transmitting apparatus and wireless receiving apparatus

Disclosure is related to a reconfigurable sorter and a method of sorting using the sorter. The reconfigurable sorting method is adapted to the sorter essentially consisting of multiple serially-connected comparison units. The each comparison unit includes two registers. The sorter is particularly a reconfigurable device according to the number of sorted numerals. According to the exemplary embodiment, an input mode is initiated firstly. Initial values are set to the registers. The numerals are sequentially inputted to the registers. At the input mode, the values in the registers may be shifted if necessary and mutually compared in every comparison unit. The values in the registers of every comparison unit may be swapped based on the comparison. At output mode, the numerals are outputted sequentially. The values in the registers are shifted and swapped until all numerals are completely outputted. The output appears the sorted numerals with low timing latency.

Reconfigurable sorter and method of sorting

A method for signal estimation and compensation and an apparatus using the same, adapted for estimating and compensating an imbalance effect between an in-phase path and a quadrature path of an Orthogonal Frequency Division Multiplexing (OFDM) communication system are provided. The method includes the following steps: receiving a signal, and using a plurality of symbols in a plurality of time frame to generate a plurality of balance coefficient groups, wherein every balance coefficient group includes a plurality of balance coefficient candidates; deriving a balance coefficient according to the balance coefficient set; and compensating the signal according to the balance coefficient.

Method for signal estimation and compensation and apparatus using the same

An all-digital clock generator includes a digitally-controlled clock generator and a processing unit. The digitally-controlled clock generator generates a clock signal in response to an enable signal and a digital signal. The processing unit has a frequency multiplier and a reference signal having a period, digitizes the period to generate a quantized signal, generates the digital signal according to the quantized signal and the frequency multiplier, and generates the enable signal according to the reference signal, the clock signal and the frequency multiplier.

Time-to-digital converter and digital-controlled clock generator and all-digital clock generator

A MIMO detection method for a receiver in a MIMO system using N-QAM for modulation, the MIMO detection method including generating a plurality of symbol vector sets and a plurality of search radiuses, selecting a candidate symbol vector set corresponding to a highest level of a multilevel structure of N-QAM constellation, generating a search space corresponding to a lower level of the multilevel structure of N-QAM constellation according to the selected candidate symbol vector set, confirming which level the search space corresponds to, and generating a detection signal according to the search space when the level of the search space is the lowest level of the multilevel structure of the N-QAM constellation.

Multilevel cluster-based MIMO detection method and MIMO detector thereof

Growing community of inventors

Hsinchu, Taiwan

Terng-Yin Hsu