Telefonaktiebolaget Lm Ericsson (Publ)

Terje Egeland

Per Anders Holmberg

Lars-Örjan Kling

Sten E Johnson

Erik B Friman

Lars-&Ouml;rjan Kling

Leif Johansson

Nils Ola Linnermark

Magnus Carlsson

Peter Norrman

Karl Oscar Joachim Str&ouml;mbergson

Hans E Sundell

Sten Edward Johnson

Karl Oscar Joachim Strömbergson

The present invention discloses a processor system comprising a processor () and at least a first memory () and a second memory (). The first memory () is normally faster than the second one, and means for memory allocation () perform the periodically static allocation of data into the first memory (). The means for memory allocation () are run-time updateable by software. An execution profiling section () is provided for continuously or intermittently providing execution data used for updating the means for memory allocation (). According to the invention, the memory allocation is performed on a variable or record () level. The means for memory allocation preferably use linking tables () supporting dynamic software changes. The first memory () is preferably an SRAM, connected to the processor by a dedicated bus ().

Static cache

The invention is directed toward a multiprocessing system having multiple processing units. For at least one of the processing units in the multiprocessing system, a first job signal is assigned to the processing unit for speculative execution of a corresponding first job, and a further job signal is assigned to the processing unit for speculative execution of a corresponding further job. The speculative execution of said further job is initiated when the processing unit has completed execution of the first job. If desirable, even more job signals may be assigned to the processing unit for speculative execution. In this way, multiple job signals are assigned to the processing units of the processing system, and the processing units are allowed to execute a plurality of jobs speculatively while waiting for commit priority. By assigning multiple job signals for speculative execution by one or more processing units, the effects of variations in execution time between jobs are neutralized, and the overall performance of the processing system is substantially improved.

Multiple job signals per processing unit in a multiprocessing system

The present invention relates to multiprocessing systems in which signals or processes are scheduled in order of their priority level. The invention is based on batch-wise acceptance and scheduling of job signals, and utilizes at least one delay queue for temporarily storing job signals to the processing system before they are accepted for scheduling. The processing system further comprises circuitry for batch-wise insertion of the temporarily stored job signals into the job scheduler of the multiprocessing system. In this way, the utilization of the parallel processing units is increased and the number of changes between different priority levels in the multiprocessing system is minimized.

Batch-wise handling of signals in a processing system

A method and apparatus for determining what program shall utilize a rapid access memory in a computer working with a plurality of programs and having a conventional slow access (NM) memory and a rapid access memory (CM), characterized in that during a test period there is registered for each program the number of instructions in the program requiring access to the memory, this number being divided by the whole memory space required by a program, the quotients formed after each other in this way being compared with each other and for the program with the highest quotient the memory content is transferred from the slow access memory to the rapid access memory. For each program there is registered with the aid of a counter (RF) the number of instructions requiring access to the slow access memory (NM). This number is divided with the aid of a measuring circuit (R1, R2, JR, KB) by the entire memory space for the respective program noted in a space memory (SM). For the program with the highest quotient the memory content is transferred from the relatively slow access memory (NM) to the rapid access memory (CM). An address memory (AM) is arranged, and for the program information transferred from the slow access memory (NM) to the rapid access memory (CM) the address memory reads out the starting address of the program information in the rapid access memory (CM) on addressing a starting address in the slow access memory (NM).

Method and apparatus for determining in a computer which of a number of

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Värmdö, Sweden

Terje Egeland