Apple Inc.

Intrinsity, Inc.

International Business Machines Corporation

Motorola Corporation

Evsx, Inc.

Other

Terence M Potter

James S Blomgren

Stephen C Horne

Andrew M Havlir

Anthony M Petro

Michael R Seningen

Benjiman L Goodman

Robert D Kenney

Liang-Kai Wang

Yoong Chert Foo

Christopher Hans Olson

Richard Warren Schreyer

Justin A Hensley

Christopher A Burns

Brian K Reynolds

Anjana Rajendran

Ralph Clay Taylor

Timothy A Elliott

Jeffrey T Brady

Paul C Rossbach

Timothy A Olson

Frank W Liljeros

Thomas Alan Hoy

Aaftab A Munshi

John Stephen Muhich

Michael Imbrogno

William V Miller

Alexander K Kan

Karl D Mann

Dimitri Tan

James J Ding

Timothy S Leight

Jeffrey S Brooks

Charles Roberts Moore

Tatsuya Iwamoto

Fritz A Boehm

Kutty Banerjee

Robert Thaddeus Golla

Christopher L Spencer

Thomas L Thomas, Jr

Michael A Geary

Betty Y Kikuta

Liang Xia

Justin Friesenhahn

Mark I Luffel

Sivayya V Ayinala

Jeffrey A Lohman

James Han Wang

Robert T Golla

Robert A Drebin

Gokhan Avkarogullari

Bradley Gene Burgess

Yu P Sun

Michael Thomas Vaden

Jonathan M Redshaw

Anthony P DeLaurier

Ali Rabbani Rankouhi

Winnie W Yeung

Benjamin Bowman

Jon A Loschke

David James Martens

Michael J Swift

Pradeep Kumar Dubey

Sergio V Tota

Aroun Demeure

Cheng Li

Owen C Anderson

Michael D Carlson

Nicolas Xavier Pena

Tan V Chu

Max J Batley

Xiao-Long Wu

Adam J Smith

Sheenam Jayaswal

Vinod Reddy Nalamalapu

Donald R Desota

David Domenic Putti

Jeffrey M Broton

Daniel Chen Chow

Chih-Jui Ray Peng

Betty Yooko Kikuta

Christopher G Martin

Douglas C Youngwith

Mark D Earl

Laura A Potter

Techniques are disclosed relating to private memory management using a mapping thread, which may be persistent. In some embodiments, a graphics processor is configured to generate a pool of private memory pages for a set of graphics work that includes multiple threads. The processor may maintain a translation table configured to map private memory addresses to virtual addresses based on identifiers of the threads. The processor may execute a mapping thread to receive a request to allocate a private memory page for a requesting thread, select a private memory page from the pool in response to the request, and map the selected page in the translation table for the requesting. The processor may then execute one or more instructions of the requesting thread to access a private memory space, wherein the execution includes translation of a private memory address to a virtual address based on the mapped page in the translation table. The mapping thread may be a persistent thread for which resources are allocated for an entirety of a time interval over which the set of graphics work is executed.

Private memory management using utility thread

Techniques are disclosed relating to storage techniques for fragment data. In some embodiments, one or more storage circuits are configured to store sample color data for processing by shader processors including a data structure that includes first and second elements configured to store color data for first and second colors, respectively. In some embodiments, control circuitry is configured to generate color state metadata to map samples in a region of pixels to colors in elements of the data structure, including to map multiple samples to the first element of the data structure. In some embodiments, control circuitry is configured to access the color state metadata to determine a mapped element of the data structure for a given sample and read the color data from the mapped element of the data structure. Disclosed techniques may improve, reduce or avoid duplication and thereby improve cache efficiency for accesses to color data.

Color state techniques for graphics processors

Techniques are disclosed relating to conversion operations in the context of integer and floating-point processor operations. In some embodiments, floating-point pipeline circuitry is configured to execute a single instruction to convert an N-bit integer value to an M-bit floating-point result. To execute the instruction, source modifier circuitry may generate an intermediate M-bit representation based on the N-bit integer value. Fused multiply-add circuitry may perform a fused multiply-add operation to generate the M-bit floating-point result, where the fused multiply-add operation operates on: the intermediate M-bit representation, a quantization scale factor value indicated by the instruction, and a zero-point value indicated by the instruction. In some embodiments that support down-conversion, the floating-point pipeline circuitry is also configured to execute a single instruction to convert an M-bit floating-point value to an N-bit integer result value.

Hardware support for conversion between integer and floating-point data

Techniques are disclosed relating to thread preemption in the context of memory-backed registers. In some embodiments, a memory hierarchy includes one or more cache levels and one or more memory circuits. Execution circuitry may operate on operands in architectural registers to execute instructions of threads, where data for the architectural registers is stored and backed by the memory hierarchy. Control circuitry may, in response to a context switch indication for a given thread: flush and invalidate a set of architectural register data from a first cache level and store memory page information (e.g., a page catalog base address) associated with the set of architectural register data.

Preemption techniques for memory-backed registers

Techniques are disclosed relating to dynamically allocating and mapping private memory for requesting circuitry. Disclosed circuitry may receive a private address and translate the private address to a virtual address (which an MMU may then translate to physical address to actually access a storage element). In some embodiments, private memory allocation circuitry is configured to generate page table information and map private memory pages for requests if the page table information is not already setup. In various embodiments, this may advantageously allow dynamic private memory allocation, e.g., to efficiently allocate memory for graphics shaders with different types of workloads. Disclosed caching techniques for page table information may improve performance relative to traditional techniques. Further, disclosed embodiments may facilitate memory consolidation across a device such as a graphics processor.

On-demand memory allocation

Techniques are disclosed relating to multi-stage thread scheduling. In some embodiments, processor circuitry includes multiple channel pipelines for multiple channels and multiple execution pipelines shared by the channel pipelines and configured to perform different types of operations provided by the channel pipelines. First scheduler circuitry may arbitrate among threads to assign threads to channels. Second scheduler circuitry may arbitrate among channels to assign an operation from a given channel to a given execution pipeline. The execution pipelines may provide backpressure information to the first scheduler circuitry based on execution status and the first scheduler circuitry may adjust priority of a thread for assignment to a channel based on the backpressure information. Disclosed techniques may reduce channel conflicts and starvation for execution resources.

Multi-stage thread scheduling

Techniques are disclosed relating to operand routing among SIMD pipelines. In some embodiments, an apparatus includes a set of multiple hardware pipelines configured to execute a single-instruction multiple-data (SIMD) instruction for multiple threads in parallel, wherein the instruction specifies first and second architectural registers. In some embodiments, the pipelines include execution circuitry configured to perform operations using one or more pipeline stages of the pipeline. In some embodiments, the pipelines include routing circuitry configured to select, based on the instruction, a first input operand for the execution circuitry from among: a value from the first architectural register from thread-specific storage for another pipeline and a value from the second architectural register from thread-specific storage for a thread assigned to another pipeline. In some embodiments, the routing circuitry may support a shift and fill instruction that facilitates storage of an arbitrary portion of a graphics frame in one or more registers.

SIMD operand permutation with selection from among multiple registers

Techniques are disclosed relating to cache footprint management. In some embodiments, execution circuitry is configured to perform operations for instructions from multiple threads in parallel. Cache circuitry may store information operated on by threads executed by the execution circuitry. Scheduling circuitry may arbitrate among threads to schedule threads for execution by the execution circuitry. Tracking circuitry may determine one or more performance metrics for the cache circuitry. Control circuitry may, based on the one or more performance metrics meeting a threshold, reduce a limit on a number of threads considered for arbitration by the scheduling circuitry, to control a footprint of information stored by the cache circuitry. Disclosed techniques may advantageously reduce or avoid cache thrashing for certain processor workloads.

Cache footprint management

Techniques are disclosed relating to processor communications fabrics. In some embodiments, a processor includes multiple client circuitry and fabric circuitry that includes at least first and second instances of a tile. The tile may include: client inputs configured to interface with client circuits, tile inputs configured to interface with one or more other tile instances, and communication resources assignable to the client inputs and tile inputs. The communications resources may include: multiple internal links, client outputs configured to interface with client circuits, and tile outputs configured to interface with one or more other tile instances. Control circuitry may, in a given cycle, assign communication resources of a given tile instance to at least a portion of the client inputs and tile inputs for a next cycle, based on priority information. The control circuitry may update priority information based on assignment results over multiple cycles.

Tiled processor communication fabric

Disclosed techniques relate to memory space management for graphics processing. In some embodiments, first and second graphics cores are configured to execute instructions for multiple threadgroups. In some embodiments, the threads groups include a first threadgroup with multiple single-instruction multiple-data (SIMD) groups configured to execute a first shader program and a second threadgroup with multiple SIMD groups configured to execute a second, different shader program. Control circuitry may be configured to provide access to data stored in memory circuitry according to a shader memory space. The shader memory space may be accessible to threadgroups executed by the first graphics shader core, including the first and second threadgroups, but is not accessible to threadgroups executed by the second graphics shader core. Disclosed techniques may reduce latency, increase bandwidth available to the shader, reduce coherency cost, or any combination thereof.

Graphics memory space for shader core

Techniques are disclosed relating to specifying memory consistency constraints. In some embodiments, an instruction may specify, for a memory operation, a type of memory consistency and a scope at which to enforce the type of consistency. For example, these fields may specify whether to sequence memory accesses relative to the operation at one or more of multiple different cache levels based on the type of memory consistency and the scope.

Memory consistency in memory hierarchy with relaxed ordering

Techniques are disclosed relating to context switching in a SIMD processor. In some embodiments, an apparatus includes pipeline circuitry configured to execute graphics instructions included in threads of a group of single-instruction multiple-data (SIMD) threads in a thread group. In some embodiments, context switch circuitry is configured to atomically: save, for the SIMD group, a program counter and information that indicates whether threads in the SIMD group are active using one or more context switch registers, set all threads to an active state for the SIMD group, and branch to handler code for the SIMD group. In some embodiments, the pipeline circuitry is configured to execute the handler code to save context information for the SIMD group and subsequently execute threads of another thread group. Disclosed techniques may allow instruction-level context switching even when some SIMD threads are non-active.

Instruction-level context switch in SIMD processor

Growing community of inventors

Austin, TX, United States of America

Terence M Potter