Xilinx, Inc.

Lsi Corporation

Lsi Logic Corporation

Terence J Magee

Cheng-Gang Kong

Derrick Sai-Tang Butt

Thomas Hughes

Xiaoqian Zhang

Jayant Mittal

Dhruv Choksey

Richard William Swanson

Christopher D Paulson

Qi Zhang

Hui-Yin Seto

Nicholas J Sawyer

Srinivas Vura

Asim A Patel

Sathappan Ravi

An example method of calibrating a source-synchronous system includes: performing initial calibration of a source-synchronous receiver, which is configured to receive data signals and a strobe, to determine an initial strobe delay and initial data delays; setting a strobe delay circuit that delays the strobe to have the initial strobe delay and data delay circuits that delay the data signals to have the initial data delays; measuring first data eye margins of the data signals at a first time; calculating metrics for the data signals based on the first data eye margins; and measuring second data eye margins of the data signals at a second time; and updating the data delay circuits and the strobe delay circuit based on the second data eye margins and the metrics.

Recalibration of source synchronous systems

An intersymbol interference (ISI) compensation circuit includes a data input for receiving an input data signal including a plurality of bits. An adjustment circuit is configured to adjust bit periods of the bits to generate a first adjusted signal and a second adjusted signal. A sampling circuit is configured to generate a first sample signal by sampling the first adjusted signal, and generate a second sample signal by sampling the second adjusted signal. A decision generation circuit is configured to provide a first decision for a first bit. The first decision provides a chosen adjusted signal that is one of the first and second adjusted signals. A selection circuit is configured to determine a compensated value of the first bit based on a chosen sample signal that is one of the first and second sample signals. The chosen sample signal is generated by sampling the chosen adjusted signal.

Method and apparatus for intersymbol interference compensation

In an apparatus relating generally to the communication of data, a first and a second receive path block are respectively coupled to receive a first and a second data stream. A clock signal source is coupled to provide at least one clock signal to each of the first and the second receive path block. A control block is coupled to receive a first output signal pair and a second output signal pair from the first and the second receive path block, respectively. The first output signal pair includes a first crossing signal and a first data signal. The second output signal pair includes a second crossing signal and a second data signal. The control block is configured to provide first and second delay adjustment signals respectively to the first and second receive path blocks, to adjust delays of the first and second data streams, respectively.

High-speed serial data interface for a physical layer interface

In an example, a control device includes a data path, a clock path, a multiplexing circuit, and a calibration unit. The data path comprises a data delay unit coupled to a data input of a sampling circuit. The clock path comprises a clock delay unit coupled to a clock input of the sampling circuit. The multiplexing circuit selectively couples a reference clock or a data bus to an input of the data delay unit, and selectively couples the reference clock or a source clock to an input of the clock delay unit. The calibration unit is coupled to a data output of the sampling circuit. The calibration unit is operable to adjust delay values of the data delay unit and the clock delay unit based on the data output of the sampling circuit to establish and maintain a relative delay between the data path and the clock path.

Calibration in a control device receiving from a source synchronous interface

In an example, a memory control device includes an output circuit, an output delay unit, and a write-levelization controller. The output circuit is coupled to provide an output signal comprising a data signal or data strobe signal for a synchronous dynamic random access memory (SDRAM) system having a plurality of ranks. The output delay unit is coupled to apply an output delay to a bitstream to be transmitted to generate the output signal. The output delay includes an aggregate of a de-skew delay and a write-levelization delay. The write-levelization delay controller is coupled to adjust the write-levelization delay for each write transaction to the SDRAM system of a plurality of write transactions based on a selected rank of the plurality of ranks. The de-skew delay is the same across the plurality of ranks for each of the plurality of write transactions.

Dynamic selection of output delay in a memory control device

A data interface enabling the calibration of input data comprises a first data receiver having a first plurality of input data lines coupled to receive a corresponding first plurality of data bits associated with a data bus, the first data receiver having a first control circuit enabling calibration of the first plurality of input data lines; and a second data receiver having a second plurality of input data lines coupled to receive a corresponding second plurality of data bits associated with the data bus, the second data receiver having a second control circuit enabling calibration of the second plurality of data lines. The first plurality of input data lines of the first data receiver are calibrated in parallel with the second plurality of input data lines of the second data receiver.

Receivers and methods of enabling the calibration of circuits receiving input data

A method, non-transitory computer readable medium and circuit for gating a strobe (DQS) signal are disclosed. The method sends a read command to a memory, sends a strobe clock signal after the read command is sent and before the DQS signal is received from the memory, wherein the strobe clock signal comprises a duration equal to a duration of the DQS signal, gates the DQS signal based on the strobe clock signal to generate a positively gated strobe signal for indicating a rising edge of the DQS signal, wherein the gating is performed during a pre-amble of the DQS signal and generates a negatively gated strobe signal based on the positively gated strobe signal for indicating a falling edge of the DQS signal.

Method and apparatus for gating a strobe signal from a memory and subsequent tracking of the strobe signal over time

Systems, devices, and circuits for source-synchronous memory interfaces are disclosed. For example, a device includes a first NAND gate with an input for receiving a serial mode enable signal. In addition, the device also includes a second NAND gate with an input for receiving a forwarded strobe signal and an input for receiving an output of the first NAND gate. The device also includes a third NAND gate with an input for receiving a data strobe signal, and an XNOR gate with an input for receiving an output of the second NAND gate and an input for receiving an output of the third NAND gate.

Read clock forwarding for multiple source-synchronous memory interfaces

A method, non-transitory computer readable medium and apparatus for synchronizing a clock signal data path, a write strobe signal data path and a write data signal data path are disclosed. The method determines an amount of phase shift between the clock signal data path and the write strobe signal data path and between the clock signal data path and the write data signal data path, gates a clock signal to generate strobe clock signals that are phase shifted by at least one phase shift, applies a fine phase shift to the strobe clock signals where the strobe clock signals have an overall phase shift that is approximately equal to the amount of phase shift, and synchronizes a launch of the clock signal data path, the write strobe signal data path, and the write data signal data path using the strobe clock signals with the overall phase shift.

Method and apparatus for VT invariant SDRAM write leveling and fast rank switching

A system and method for interfacing a memory controller and a source synchronous memory utilizing a generic low power strobe. A set of double rate (2&#xd7;) strobes can be generated by gating a continuous double rate clock in order to enable the set of double rate strobes only for duration of a data transfer from controller to the memory. The data and control from a SDR continuous single rate (1&#xd7;) clock domain with respect to the memory controller can be moved to a set of double rate clock domain by sampling with the set of double rate strobes. The phase of the set of double rate strobes can be shifted in relation to the continuous single rate clock and a phase relationship of the generated synchronous signals to the memory can be dynamically switched by changing the phase of the set of double rate strobes. The set of double rate clock domain enables each bit-slice to be independently programmed to generate an output to the memory at each phase relative to the controller single rate clock.

Generic low power strobe based system and method for interfacing memory controller and source synchronous memory

A non-linear common coarse delay system and method for delaying a data strobe in order to preserve fine delay accuracy and compensate PVT (Process, Voltage, and Temperature) variation effects. A common coarse delay and a fine delay can be initialized to a quarter-cycle delay for shifting a read output DQS (Data Queue Strobe) associated with a memory device in order to sample a read output DQ (Data Queue) within a physical layer. The fine delay can be programmed from minimum to maximum delay with fixed linear increments at each delay step in order to determine the resolution and accuracy of the delay. An optimum delay size of both the coarse and the fine delay can be determined based on an application slowest frequency of operation. A spare coarse delay and a functional coarse delay can be trained in association with a spare fine delay and the functional fine delay can be updated in order to monitor the process, voltage, and temperature variation effects.

Non-linear common coarse delay system and method for delaying data strobe

A memory interface physical layer macro including one or more embedded input/output (I/O) buffers, one or more memory interface hardmacros and control logic. The one or more embedded input/output (I/O) buffers support a plurality of I/O supply voltage levels. The one or more memory interface hardmacros are coupled to the one or more embedded I/O buffers. The control logic controls the one or more hardmacros and the one or more I/O buffers.

Multiple memory standard physical layer macro function

A memory interface subsystem including a write logic and a read logic. The write logic may be configured to communicate data from a memory controller to a memory. The read logic may be configured to communicate data from the memory to the memory controller. The read logic may comprise a plurality of physical read datapaths. Each of the physical read datapaths may be configured to receive (i) a respective portion of read data signals from the memory, (ii) a respective read data strobe signal associated with the respective portion of the received read data signals, (iii) a gating signal, (iv) a base delay signal and (v) an offset delay signal.

Configurable high-speed memory interface subsystem

A method for glitch-free updates of a standard cell-based programmable delay including the steps of (A) generating an output signal in response to an input signal and a plurality of first control signals and (B) generating the plurality of first control signals in response to the output signal and a plurality of second control signals. The output signal may include a delayed version of the input signal. An amount of delay between the input signal and the output signal may be determined based upon the plurality of first control signals.

System for glitch-free delay updates of a standard cell-based programmable delay

The present invention is directed to a method for compensating for process, voltage, and temperature variation without complex online/offline swapping of data paths requiring a dedicated FIFO(First-in First-out) buffer design. Delay cells are trained for each clock path (namely a Functional delay) and a spare delay cell is trained. A ratio is calculated for each Functional delay cell by dividing the Functional delay cells' setting into the spare delay cells' one-fourth cycle setting. These ratios reflect any process variation. Functional mode is then entered and a Master-Slave approach switched to, during which the spare delay cell repeats the training sequence continuously while the Functional delay cells delay the clocks from the RAM(Random Access Memory). Each Functional delay cell is updated at the end of each training sequence of the spare delay cell, compensating for voltage and temperature change, by dividing the ratio into the new spare delay cell one-fourth cycle setting.

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San Francisco, CA, United States of America

Terence J Magee