Texas Instruments Corporation

Terence G Blake

Theodore Warren Houston

Hsindao E Lu

Bernhard H Andresen

Mishel Matloubian

Frederick G Wall

Cheng-Eng D Chen

Anand Seshadri

Jarrod Eliason

A SRAM cell wherein the pull up load of the cell is inherent ferroelectric leakage. The power down writeback may include boosting the word line. The power down writeback may also include discharging the plate from Vto ground. Furthermore, the plate is held high during read and write operations.

Non-volatile SRAM

An output buffer with switching PMOS drivers (10) is disclosed. According to one embodiment, output buffer (10) includes a first output driver (62) and a second output driver (68). A first output cascode (64) coupled to the first output driver (62) protects the gate oxide of the first output driver (62) from voltage changes on the output (16). A second output cascade (66) coupled to the second output driver (68) protects the gate oxide of the second output driver (68) from voltage changes on the output (16). A level shifter (30) includes multiple cascode devices (46, 48, 50, 52) and switches the first output driver (62) according to the values of a data input (12) and an enable input (14). Switching circuitry (60) coupled to the second output cascode (64) allows the first output cascode (64) to protect the gate oxide of the first output driver (62) and provides extra drive for the output buffer (10).

Output buffer with switching PMOS drivers

According to one embodiment of the present invention, an output buffer (200) includes a first output driver (86) having a gate oxide protected from voltage changes on an output (16). A second output driver (88) also has a gate oxide protected from voltage changes on the output (16). A level shifter (60) includes at least one cascode device (66, 68, 70, 72) and switches the first output driver (86) according to the values of a data input (12) and an enable input (14). A bias-generation circuit (300) generates a quasi-failsafe voltage that is approximately equal to a chip core voltage when a power supply (4) is supplying the chip core voltage and equal to a portion of the chip core voltage when the power supply (4) is not supplying the chip core voltage. The bias-generation circuit (300) is coupled to a first output cascode (80) coupled to the first output driver (86), to a second output cascode (84) coupled to the second output driver (88), or to the cascode device (66, 68, 70, 72) of the level shifter (60).

Output buffer having quasi-failsafe operation

According to one embodiment of the present invention, an output buffer (200) includes a first output driver (86) and a second output driver (88). A first output cascode (80) coupled to the first output driver (86) protects the gate oxide of the first output driver (86) from voltage changes on the output (16). A second output cascode (84) coupled to the second output driver (88) protects the gate oxide of the second output driver (88) from voltage changes on the output (16). A level shifter (60) includes multiple cascode devices (66, 68, 70, 72) and switches the first output driver according to the values of a data input (12) and an enable input (14). A first testability device (202, 204, 206, 208) coupled to a cascode device (66, 68, 70, 72) of the level shifter (60) generates a current in response to failure of the cascode device (66, 68, 70, 72).

Output buffer providing testability

A compact capacitor for use in a small memory cell in high density memories is disclosed. Such a capacitor in the cross-coupling of cross-coupled inverters in the memory cell improves single event upset hardness. The subject capacitor in its preferred embodiment is a MOS capacitor with both n+ and p+ connections to the capacitor channel so as to maintain a relatively high capacitance for both positive and negative capacitor gate voltages.

Memory cell with capacitance for single event upset protection

An on-chip transient event detector (FIG., 1) is fabricated onto an integrated circuit chip to provide rapid response to a detected event, such as a transient radiation dose or other condition that can cause transient current pulses. The transient event detector includes a detector circuit 10 that includes a narrow p-channel FET (12), and a wide n-channel FET (14). These detector transistors are coupled together and biased so that the narrow-channel transistor is normally on and the wide-channel transistor is normally off. A transient event, such as a photocurrent induced by radiation, causes a current pulse in the normally off wide-channel transistor that is sufficiently greater than the current in the narrow-channel transistor to cause a change in logic output, providing an event signal. The event signal can be used to disable memory WRITE operations during the transient event. The detector circuit can be integrated with an on-chip time-delay circuit (30) to provide a time-delayed system reset signal.

On-chip transient event detector

Silicon-on-insulator mesa steps cause high resistance in polycrystalline material because of the lack of silicide coverage. In a gate or word line, for instance, this accounts for a large resistance. By connecting the mesas through the body nodes of adjacent transistors, all mesa steps in a polycrystalline semiconductor gate are eliminated. Thus, gate or word line resistance is reduced.

SOI layout for low resistance gate

A silicon-on-insulator MOS transistor (100) is disclosed which has contact regions on both the source (6) and drain (8) sides of the gate electrode (10) for (36,38) potentially making contact to the body node (12) from either side. Each contact region (36,38) is of the same conductivity type as the body node (12), (for example, a p-type region for an n-channel transistor), and may be formed by blocking all source/drain implants from the contact regions (36,38), so that the contact region (36,38) remains substantially with the same doping concentration as the of the body region (12). A mask is provided prior to silicidation so that the contact regions (36,38) on either side of the gate electrode (12) are not connected by silicide to the adjacent source/drain doped regions (6,8). Once a side is selected to be the source of the transistor, ohmic connection is then made between the abutting source region (6) and the contact region (36) by way of contacts (22,23) through an overlying interlevel dielectric (40) and metallization (25). A second embodiment of the transistor (200) is disclosed which provides such contact with reduction in the channel width, by allowing the lightly-doped drain extension of the source (19) and drain (18) to be present between the contact region (36,37,38) on both sides of its gate so that all of the contact regions on the mesa are connected through the body nodes of the transistors. A single body-to-source node connection can thus provide body node bais for all of the transistors on the mesa.

Silicon-on-insulator transistor with selectable body node to source node

A memory cell is disclosed comprising cross-coupled inverters including gated diodes connected in the cross-coupling which increase the memory cell's resistance to single event upset. The layouts for constructing such a memory cell, which optimize READ and WRITE speeds, are also disclosed.

SEU hardened memory cell

An MOS transistor is disclosed which has a guard ring for prevention of source-to-drain conduction through the isolation oxide after exposure to ionizing radiation. In the described example of an n-channel transistor, a p+ region is formed at the edges of the source region in a self-aligned fashion relative to the gate electrode so as not to extend under the gate to contact the drain region. This p+ region forms a diode which retards source-drain conduction even if a channel is formed under the isolating field oxide where the gate electrode overlaps onto the field oxide. The structure may be silicided for improved series resistance. An example of the transistor formed in an SOI configuration is also disclosed.

MOS transistor with improved radiation hardness

A silicon-on-insulator MOS transistor is disclosed which has an implanted region on the source side of the gate electrode for making contact to the body node. A contact region of the same conductivity type as the body node, (for example, a p+ region for an n-channel transistor) is formed within the source region in a self-aligned fashion relative to the gate electrode. Ohmic connection is then made between the abutting source region and the contact region, for example by way of silicidation. Since the contact region is of the same conductivity as the body node, a non-rectifying ohmic contact is made between the source and body nodes of the transistor. For SOI CMOS technology, no additional mask steps are required for formation of the contact, as the source/drain implant masks required for the masking of opposite conductivity type regions can be used for the formation of the contact region.

Silicon-on-insulator transistor with body node to source node connection

A process for making a silicon-on-insulator MOS transistor is disclosed which includes forming an implanted region on the source side of the gate electrode for making contact to the body node. A contact region of the same conductivity type as the body node, (for example, a p+ region for an n-channel transistor) is formed within the source region in a self-aligned fashion relative to sidewall oxide filaments on the source side of the gate electrode. The lightly-doped drain extension of the source region remains disposed between the contact region and the body node at the surface, but the contact region extends below the depth of the lightly-doped drain region to make contact to the body node. Ohmic connection is then made between the abutting source region and the contact region, for example by way of silicidation. Since the contact region is of the same conductivity as the body node, a non-rectifying ohmic contact is made between the source and body nodes of the transistor. For SOI CMOS technology, no additional photolithographic or implant steps are required for formation of the contact, as the source/drain implant masks required for the masking of opposite conductivity type regions and the associated implants can be used in the formation of the contact region.

Process for making high performance silicon-on-insulator transistor with

The rate of single event upset in a memory cell is reduced by a pair of active devices in the cross-coupling between a pair of inverters. The active devices are controlled by voltages internal to the memory cell such that writing into the cell is not slowed significantly.

Growing community of inventors

Dallas, TX, United States of America

Terence G Blake