International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Globalfoundries U.S. 2 LLC

Adeia Semiconductor Bonding Technologies Inc.

Elpis Technologies Inc.

Globalfoundries U.S. 2 LLC Company

Terence B Hook

Brent A Anderson

Tenko Yamashita

Junli Wang

Bruce Bennett Doris

Joshua M Rubin

Kangguo Cheng

Kirk David Peterson

Huiming Bu

Anthony K Stamper

Reinaldo Ariel Vega

Takashi Ando

Michael A Guillorn

Robert Russell Robison

Ruqiang Bao

Jeffrey Bowman Johnson

Xuefeng Liu

Ali Khakifirooz

Edward J Nowak

Robert J Gauthier, Jr

Balasubramanian Pranatharthiharan

Douglas Duane Coolbaugh

Xin Miao

John J Ellis-Monaghan

Fee Li Lie

Baozhen Li

Hayden C Cranford, Jr

Hon-Sum Philip Wong

William Joseph Murphy

Veeraraghavan S Basker

Vijay Narayanan

Robert Mark Rassel

Edmund Juris Sprogis

Randy William Mann

Ebenezer E Eshun

Jeffrey Scott Brown

Chen Zhang

Chun-chen Yeh

Jeffrey W Sleight

Nicolas J Loubet

Tak H Ning

Hemanth Jagannathan

Lars W Liebmann

Timothy Dooling Sullivan

Su Chen Fan

Robert H Dennard

Pranita Kulkarni

Rajasekhar Venigalla

Gauri V Karve

William F Clark, Jr

Jason D Hibbeler

James Spiros Nakos

Christopher Stephen Putnam

Thomas L McDevitt

Ruilong Xie

Effendi Leobandung

Theodorus E Standaert

William R Tonti

Rajiv V Joshi

Kerry Bernstein

Hsueh-Chung Chen

Yann Mignot

Wilfried Haensch

JunJun Li

Matthew Joseph Breitwisch

Pranita Kerber

Richard Quimby Williams

Louis C Hsu

Lawrence Alfred Clevenger

Jack Allan Mandelman

Ghavam G Shahidi

Louis L Hsu

Chung H Lam

Claude Louis Bertin

Steven H Voldman

Shogo Mochizuki

Arne Watson Ballantine

John Atkinson Fifield

Souvick Mitra

Andrew Herbert Simon

Robert K Leidy

Wilbur David Pricer

Stephen Victor Kosonocky

Bomy A Chen

Robert C Wong

Wei Hwang

Albert Manhee Chu

James Albert Slinkman

Anthony Richard Bonaccio

Li-Kong Wang

Anthony Correale, Jr

Anthony I Chou

Indira P Seshadri

Roger Allen Booth, Jr

Kiran V Chatty

Stuart A Sieg

Henry K Utomo

Roger Allan Quon

Renata A Camillo-Castillo

Erik L Hedberg

A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

High aspect ratio contact structure with multiple metal stacks

A set of transistor elements includes a substrate of a first doping type and a first well and a second well, both of a second doping type and both formed on the substrate. The set of transistor elements also includes a first complementary transistor cell and a second complementary transistor cell. The set of transistor element also includes an anti-propagation region of the first doping type between the first well and the second well.

Size-efficient mitigation of latchup and latchup propagation

Apparatus for mitigating latch-up within semiconductor devices. A semiconductor device includes a first conductor, a second conductor, and a first gate conductor. The first conductor extends in a first direction, receives a first power supply signal, and is connected to a first electrode. The second conductor extends in the first direction, receives a second power supply signal different from the first power supply signal, and is connected to a second electrode. The first conductor is offset from the second conductor in a second direction perpendicular to the first direction in a top-down view to mitigate formation of parasitic devices within the semiconductor device electrically connecting the first conductor with the second conductor. The first gate conductor is disposed adjacent to the first conductor and the second conductor, is disposed on the first electrode and the second electrode, and receives an input signal.

Semiconductor device design mitigating latch-up

A semiconductor including a short channel device including a vertical FET (Field-Effect Transistor), and a long channel device comprising a second vertical FET integrated with the short channel device. The long channel device including a plurality of short channel devices.

Long channel and short channel vertical FET co-integration for vertical FET VTFET

A heat pipe is provided as an electrically inactive structure to dissipate heat that is generated by vertically stacked field effect transistors (FETs). The heat pipe is present in an electrically inactive device area which is located adjacent to an electrically active device area that includes the vertically stacked FETs. The heat pipe includes at least one vertical interconnect structure that continuously extends between each tier of the vertically stacked FETs.

Heat pipe for vertically stacked field effect transistors

One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

Gate-all-around field effect transistor having multiple threshold voltages

Aspects of the invention include systems and methods for implementing a CMOS circuit design that uses a sea-of-gates fill methodology to provide latch-up avoidance. A non-limiting example computer-implemented method includes identifying a fill cell in the circuit design. The fill cell can include a power rail, a ground rail, and a field-effect transistor (FET) electrically coupled to the power rail through a via. The method can include disconnecting the via from the power rail and moving the via to a disconnected node in the fill cell. Moving the via decouples a source or drain of the fill cell from a well of the fill cell, preventing latch-up while maintaining via and metal shape density.

Latch-up avoidance for sea-of-gates

Provided are techniques for generating fully depleted silicon on insulator (SOI) transistor with a ferroelectric layer. The techniques include forming a first multi-layer wafer comprising a semiconductor layer and a buried oxide layer, wherein the semiconductor layer is formed over the buried oxide layer. The techniques also including forming a second multi-layer wafer comprising the ferroelectric layer, and bonding the first multi-layer wafer to the second multi-layer wafer, wherein the bonding comprises a coupling between the buried oxide layer and the second multi-layer wafer.

Fully depleted SOI transistor with a buried ferroelectric layer in back-gate

In a self-aligned fin cut process for fabricating integrated circuits, a sacrificial gate or an epitaxially-formed source/drain region is used as an etch mask in conjunction with a fin cut etch step to remove unwanted portions of the fins. The process eliminates use of a lithographically-defined etch mask to cut the fins, which enables precise and accurate alignment of the fin cut.

Methods of performing fin cut etch processes for FinFET semiconductor devices

A method for fabricating a semiconductor device including multiple pairs of threshold voltage (Vt) devices includes forming a stack on a base structure having a first region corresponding to a first pair of Vt devices, a second region corresponding to a second pair of Vt devices and a third region corresponding to a third pair of Vt devices. The stack includes a first dipole layer, a first sacrificial layer formed on the first dipole layer, a second sacrificial layer formed on the first sacrificial layer, and a third sacrificial layer formed on the second sacrificial layer. The method further includes forming a second dipole layer different from the first dipole layer.

Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device

A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.

Nanosheet field effect transistors with partial inside spacers

A semiconductor and a method of forming a semiconductor on a single chip, including forming a shallow trench isolation (STI) region on a short channel device and a long channel device, forming at least two vertical fins connected in the long channel device, and forming contacts on a source and drain regions for the long channel device and short channel device, wherein the contacts connect a top surface of the source or drain region for series FET (Field-Effect Transistor) connection for the long channel device.

A semiconductor device including pairs of multiple threshold voltage (Vt) devices includes at least a first region corresponding to a first pair of Vt devices, a second region corresponding to a second pair of Vt devices including a first dipole layer, and a third region corresponding to a third pair of Vt devices including a second dipole layer different from the first dipole layer.

Methods and systems for checking a wafer-level design for compliance with a rule include determining a tile area that crosses a boundary between adjacent chip layouts and that leaves at least a portion of each chip layout uncovered. It is determined that a portion of a first chip layout inside the tile area fails to comply with one or more layout design rules. The first chip layout is modified to bring non-compliant periphery chip regions into compliance, in response to the determination that the portion of the first chip layout inside the tile area fails to comply with the one or more design rules. A multi-chip wafer is fabricated that includes the chip layouts.

Checking wafer-level integrated designs for rule compliance

Growing community of inventors

Jericho, VT, United States of America

Terence B Hook