L-3 Communications Corporation

Teren G Jameson

Dan M Griffin

David J Moore

Osama Sami Haddadin

Zachary C Bagley

Scott C Smedley

Scott N Adamson

A digital signal processing (DSP) apparatus is used for processing a plurality of different signals. The DSP apparatus includes a DSP module configured to perform a DSP algorithm on samples of the signals. The DSP apparatus also has a parameter memory that includes a plurality of memory cells. The parameter memory has a signal number input and a parameter output. The parameter output is connected to the DSP module. The parameter memory is configured to output to the parameter output a parameter corresponding to a signal identifier at the signal number input.

Digital signal processing apparatus having parameter memory device and process of using such

A digital signal processing (DSP) apparatus can be used to process a serial stream of digital signal samples of a plurality of 'n' number of different signals. The DSP apparatus can include a DSP module configured to perform a DSP algorithm on digital signal samples of the signals. The DSP apparatus can have a delay memory with an 'n' number of memory cells that each corresponding to one of the signals. The delay memory can also have a digital signal sample input connected to said initial input of said DSP module, a signal-number-in input, a signal-number-out input, and a digital signal sample output connected to said delay input of said DSP module. The delay memory can be configured to store a digital signal sample at the digital signal sample input in a memory cells identified by a signal identifier at said signal-number-in input. The delay memory can also be configured to output at the digital signal sample output a digital signal sample stored in a memory cells identified by a signal identifier at the signal-number-out input.

Digital signal processing apparatus with a delay memory having a plurality of memory cells and process for using same

An interference channel equalizer for receiving and processing at least two distinct RF data signals transmitted over the same frequency to a single receiving station that has at least one receiver for each distinct transmitted RF data signal. Each receiver processes an RF data signal received by its antenna and outputs an output data signal which corresponds to one of the distinct transmitted RF data signals. Each receiver includes an antenna configured to receive an RF data signal, a demodulator, a delay block to selectively delay the received RF data signal, an interference cancellation feed forward filter that uses the received signal from another receiver to remove co-channel due to another distinct RF transmitted data signal from the signal being processed, and a decision feedback equalizer to mitigate both intersymbol and multi-path interference from the received signal being processed.

Interference channel equalizer

The present invention is directed to a decision feedback equalizer that implements a multipath delay calculator to determine the delay between a line-of-sight component of a received data signal and a reflection of the line-of-sight component. The determined delay is used to control when decisions are used within the decision feedback equalizer so that the appropriate decisions are delayed until the reflection is received. In this way, the reflection can be substantially removed from the data signal using decisions that were generated when the line-of-sight component was received. Because the correction window is limited to the time when the reflection is received, the number of taps required to perform equalization is greatly reduced resulting in a decision feedback equalizer with less circuitry or logic.

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Salt Lake City, UT, United States of America

Teren G Jameson