Intel Corporation

Teong Guan Yew

Bok Eng Cheah

Jackson Chung Peng Kong

Choong Kooi Chee

Loke Yip Foo

Chee-Yee Chung

Alex Waizman

James E Breisch

Amit Kumar Srivastava

Eng Huat Goh

Kooi Chi Ooi

Mark A Schaecher

Yee Lun Ong

The present disclosure relates to an electronic assembly including a package substrate with a first surface and an opposing second surface; a first interconnect disposed in the package substrate and extending between the first and the second surfaces; and a second interconnect disposed in the package substrate and extending between the first and the second surfaces; wherein the first interconnect comprises a first recessed side wall and the second interconnect is arranged adjacent the first recessed side wall.

Recessed vertical interconnects for device miniaturization

A chip assembly may include a package substrate that includes one or more pins. The chip assembly may also include one or more pads. The one or more pads may be electrically coupled to the one or more pins. In addition, the chip assembly may include a board that includes one or more board pads. Further, the chip assembly may include an anisotropic layer. The anisotropic layer may be positioned between the board and the one or more pads and between the board and a portion of the package substrate. In addition, the anisotropic layer may mechanically couple the board to the one or more pads and to the portion of the package substrate. Further, the anisotropic layer may electrically couple the one or more pads to the one or more board pads.

Chip assemblies

A dual-sided embedded multi-die interconnect bridge provides power and source conduits from the bridge bottom at a silicon portion, in short paths to dice on a die side of an integrated-circuit package substrate. Signal traces are in a metallization on the silicon portion of the dual-sided EMIB. Power, ground and signal vias all emanate from the dual-sided embedded multi-die interconnect bridge, with power and ground entering the bridge from central regions of the silicon portion.

Embedded dual-sided interconnect bridges for integrated-circuit packages

According to various examples, a device is described. The device may include a package substrate. The device may also include a plurality of semiconductor devices disposed on the package substrate, wherein the plurality of semiconductor devices comprises top surfaces and bottom surfaces. The device may also include a plurality of interconnects coupled to the package substrate, wherein the plurality of interconnects are adjacent to the plurality of semiconductor devices. The device may also include a flyover bridge coupled to the top surfaces of the plurality of semiconductor devices and the plurality of interconnects, wherein the flyover bridge is directly coupled to the package substrate by the plurality of interconnects, and wherein the bottom surfaces of the plurality of semiconductor devices are electrically isolated from the package substrate.

Stacked semiconductor package with flyover bridge

A port of a first integrated circuit is coupled to a first communication path. Configuration information is communicated between a connector coupled to a second device and a second integrated circuit through the port and the first communication path. The port is decoupled from the first communication path. The port is coupled to a second communication path. Data is communicated between the connector and the second integrated circuit through the port and the second communication path.

Selectively enabling first and second communication paths using a repeater

Methods, systems, and apparatuses for a foldable fabric-based semiconductor package (FFP) that can assist with charging a secondary cell are described. An FFP includes: a ground plane; a first component over the ground plane; a second component adjacent to the ground plane; a third component adjacent to the second component; a molding compound encapsulating the ground plane, the first component, the second component, and the third component; a first fabric layer on a top side of the molding compound; and a second fabric layer on a bottom side of the molding compound. Each of the first, second, and third components includes one or more semiconductor dies. The third component is electrically coupled to each of the first and second components. The first and second components can wireless charge the secondary cell. The third component can power the first and second components. The ground plane can protect against electromagnetic signals.

Foldable fabric-based packaging solution

Structures and methods are provided for dual referenced microstrip structures having low reference discontinuities between a microstrip trace referenced to a primary reference plane as compared to a microstrip trace referenced to a secondary reference plane. A method, according to one embodiment of the invention, includes the calculation of a first characteristic impedance of the dual referenced microstrip transmission line referenced to a primary reference layer, the calculation of a second characteristic impedance of the dual referenced microstrip transmission line referenced to a secondary reference layer, the calculation of an absolute value of a difference between the first and the second characteristic impedance, the comparison of the absolute value of the difference to a predetermined threshold value, and if the absolute value of the difference is greater than the predetermined threshold value, then a physical parameter associated with the characteristic impedance between the primary and secondary reference layers may be varied until the difference is reduced to less than the predetermined threshold. A structure, according to one embodiment of the invention includes a microstrip transmission line, a first conductive plane, a first dielectric layer provided between the microstrip transmission line and the first conductive plane, a second conductive plane, and a second dielectric layer provided between the first conductive plane and the second conductive plane.

Growing community of inventors

Perak, Malaysia

Teong Guan Yew