Skhynix Inc.

Teodor Vlasov

Sergei Musin

Fan Zhang

Aman Bhatia

Meysam Asadi

Yauheni Yaromenka

An encoding device and a decoding device use linear and nonlinear codes for encoding and decoding system data for a storage device. The encoding device includes a linear encoder for encoding first data to generate encoded data and a nonlinear transformer for transforming the encoded data with second data to generate output data. The first data includes data on a physical address corresponding to a logical address. The second data includes the logical address and a timestamp value indicating a version of map data mapping between the logical address and the physical address.

Encoding and decoding device for system data of storage device

A controller determines, for each read operation, a mathematical model by using a) a set function of a read threshold voltage set among the plurality of read threshold voltages and b) a set checksum value; determines a polynomial regression model based on the mathematical model; determines a parameter set by using multiple computations between input and output matrices based on the polynomial regression model; and estimates a next read threshold voltage for a next read operation based on the parameter set. The controller computes mathematical operation algorithms to replace a normal multiplication operation, a normal division operation and a normal multiplication followed by division operation.

Read threshold estimation system using calculations based on polynomial regression

A data processing system includes a host, a plurality of memory devices configured to operate in parallel and a controller including a host interface controller and a plurality of cores, which are respectively coupled to the plurality of memory devices. The controller splits a logical block address (LBA) range associated with each of the cores into a plurality of LBA groups. When it is detected that there is imbalance of workloads among the cores, the controller identifies first and second cores contributing to the imbalance of workloads and selects a first LBA group, among the range of LBAs of the first core, and selecting a second LBA group, among the range of LBAs of the second core. The controller transfers data associated with the first LBA group to the second LBA group and reroutes data initially intended for the first LBA group to the second LBA group.

Systems and methods for dynamic logical block address distribution between multicores

A memory system includes a memory device including a plurality of cells associated with multiple pages and a controller. The controller selects a read bias set in response to a read address and modifies the read bias set to generate modified read bias set using one of a plurality of modification arrays. The controller performs a read operation on the select page using the modified read bias set. For a select read bias of the read bias set, the controller accumulates a fail bit count corresponding to a read operation using a select modified read bias of the modified read bias set into the plurality of accumulators using subtraction or addition. When an absolute value of a certain accumulator of the fail bit count is greater than a threshold, the controller shifts the select read bias in a correction direction by a specific magnitude corresponding to the accumulator sign.

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Minsk, Belarus

Teodor Vlasov