International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Renesas Electronics Corporation

Elpis Technologies Inc.

Stmicroelectronics Gmbh

State University of New York

Samsung Electronics Co., Ltd.

Kabushiki Kaisha Toshiba

Adeia Semiconductor Solutions LLC

Tessera LLC

Tenko Yamashita

Kangguo Cheng

Chun-chen Yeh

Veeraraghavan S Basker

Ruilong Xie

Zuoguang Liu

Effendi Leobandung

Theodorus E Standaert

Shom Ponoth

Chen Zhang

Balasubramanian S Haran

Chun-Chen Yeh

Huiming Bu

Terence B Hook

Joshua M Rubin

Ali Khakifirooz

Hui Zang

Xin Miao

Hiroaki Niimi

Sanjay C Mehta

Takashi Ando

Chia-Yu Chen

Sivananda K Kanakasabapathy

Heng Wu

Alexander Reznicek

Shogo Mochizuki

Oleg Gluschenkov

Bruce Bennett Doris

Junli Wang

Nicolas J Loubet

Cheng Chi

Dechao Guo

Xiuyu Cai

Chanro Park

Balasubramanian Pranatharthiharan

Soon-Cheon Seo

Injo Ok

Su Chen Fan

Hyun-Jin Cho

Andres Bryant

Chung-Hsun Lin

Wilfried Haensch

Jeffrey W Sleight

Robert Russell Robison

Johnathan E Faltermeier

Juntao Li

Karthik Balakrishnan

Isaac Lauer

Praneet Adusumilli

Chun Wing Yeung

Michael A Guillorn

Ruqiang Bao

Fee Li Lie

Reinaldo Ariel Vega

Hong He

Pranita Kulkarni

Vijay Narayanan

Son Van Nguyen

Thomas N Adam

JunJun Li

Chi-Chun Liu

Steven J Bentley

Muthumanickam Sankarapandian

Shay Reboh

Darsen D Lu

Brent A Anderson

Josephine B Chang

Hemanth Jagannathan

Wenyu Xu

Jeffrey Bowman Johnson

Rajasekhar Venigalla

Dieter F Wendel

Chiahsun Tseng

Charan V Surisetty

Lawrence Alfred Clevenger

Pouya Hashemi

Robert J Gauthier, Jr

Ramachandra Divakaruni

Julien Frougier

Ying Di Zhang

Qing Liu

Zheng Xu

Jingyun Zhang

Andrew Mark Greene

Kisik Choi

Pranita Kerber

Koji Watanabe

Dongbing Shao

Jody Alan Fronheiser

Raghavasimhan Sreenivasan

Gen Tsutsui

Akira Hokazono

Ajey Poovannummoottil Jacob

Ekmini Anuja De Silva

Min Gyu Sung

Yunpeng Yin

Michael P Belyansky

Xinhui Wang

Michael John Hargrove

Dexin Kong

A plurality of transistor components, a system, and a method of forming a vertically stacked transistor structure within a wafer. The plurality of transistor components may include a first bottom transistor, where the first bottom transistor includes a channel, a gate, a source, and a drain. The plurality of transistor components may also include a first contact on top of the first bottom transistor, where the first contact is proximately connected to the first bottom transistor. The plurality of transistor components may also include a first set of stacked transistors, where the first set of stacked transistors includes a second top transistor on top of a second bottom transistor.

Dummy fin contact in vertically stacked transistors

Embodiments of present invention provide a semiconductor device. The semiconductor device includes a silicon (Si) substrate containing a set of short channel field-effect-transistors (FETs); a germanium (Ge) layer on top of the Si substrate containing a set of long channel p-type FETs (PFETs); and an oxide semiconductor layer on top of the Ge layer containing a set of long channel n-type FETs (NFETs), wherein the set of short channel FETs, long channel PFETs, and long channel NFETs are interconnected through a set of far-back-end-of-line (FBEOL) layers.

Vertically integrated semiconductor device

Provided is a read-only memory (ROM) device. The ROM device comprises a substrate that has a plurality of vertical transport field effect transistors (VFETs). The ROM device further comprises an un-activated semiconductor layer provided on each VFET. The un-activated semiconductor layer includes implanted dopants that have not been substantially activated.

Read-only memory with vertical transistors

Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

Air gap spacer formation for nano-scale semiconductor devices

A semiconductor device is provided and includes a first substrate including a first transistor; a laser reflection layer on the first transistor; and a second substrate on the laser reflection layer, the second substrate including a second transistor.

Stacked transistor structure with reflection layer

A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.

Punch through stopper in bulk finFET device

A neural network device comprises a first plurality of synapse network capacitors, wherein the synapse network capacitors of the first plurality of synapse network capacitors share a first output terminal. The neural network device further comprises a second plurality of synapse network capacitors, wherein the synapse network capacitors of the second plurality of synapse network capacitors share a second output terminal. Still further, the neural network device comprises a metal shielding disposed between the first output terminal and the second output terminal. The neural network device may be used as part of an artificial intelligence system.

Capacitor-based synapse network structure with metal shielding between outputs

One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

Gate-all-around field effect transistor having multiple threshold voltages

A semiconductor structure includes a three-dimensional stacked transistor structure including first and second field-effect transistors of a first type at a first vertical level and third and fourth field-effect transistors of a second type at a second vertical level disposed over the first vertical level. The semiconductor structure also includes a first gate structure shared between the first and second field-effect transistors at the first vertical level, a second gate structure shared between the third and fourth field-effect transistors at the second vertical level, and a gate contact shared by the first and second gate structures. The wherein the first and second gate structures are vertically aligned with another in a layout of the three-dimensional stacked transistor structure between source drain/regions of the first, second, third and fourth field-effect transistors.

Circuit wiring techniques for stacked transistor structures

Ground rule verification ('GRV') design layouts may be automatically generated based on one or more design macros. The GRV design layout may be tested based on the one or more design macros by violating one or more ground rules using one or more GRV ranges. The testing may include electrical testing of the one or more GRV design layouts based on the one or more design macros. The one or more ground rules may be automatically selected and approved the based upon a degree of violation acceptability.

Automatic generation of ground rule verification macros

A semiconductor device formed by forming a stack of alternating horizontal nanosheet layers, recessing the stack for an n-type field effect transistor (nFET), growing crystalline semiconductor adjacent to the stack, forming vertical nanosheets from the crystalline semiconductor, forming inner spacers between the vertical nanosheets, and forming a high-k metal gate structure around the horizontal nanosheets and the vertical nanosheets.

Hybrid complementary metal-oxide semiconductor field effect transistor nanosheet device

A vertical field-effect transistor includes a substrate comprising a semiconductor material; a first set of fins formed from the semiconductor material and extending vertically with respect to the substrate; and a second set of fins extending vertically with respect to the substrate, wherein ones of the second set of fins abut ones of the first set of fins. The second set of fins comprises a dielectric material.

Vertical field-effect transistor with dielectric fin extension

A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising at least a first gate structure having a first gate length, and a second VTFET stacked on the first VTFET and comprising at least a second gate structure having a second gate length that is less than the first gate length. The method includes forming, on a substrate, a first VTFET including at least a first gate structure having a first gate length. The method further includes forming a second VTFET stacked on the first VTFET and including at least a second gate structure having a second gate length that is less than the first gate length.

Reducing gate resistance in stacked vertical transport field effect transistors

A technique relates to a semiconductor device. A source or drain (S/D) contact liner is formed on one or more S/D regions. Annealing is performed to form a silicide layer around the one or more S/D regions, the silicide layer being formed at an interface between the S/D contact liner and the S/D regions. A block layer is formed into a pattern over the one or more S/D regions, such that a portion of the S/D contact liner is protected by the block layer. Unprotected portions of the S/D contact liner are removed, such that the S/D contact liner protected by the block layer remains over the one or more S/D regions. The block layer and S/D contacts are formed on the S/D contact liner over the one or more S/D regions.

Source and drain contact cut last process to enable wrap-around-contact

A semiconductor device is provided. The semiconductor device includes a metal-oxide-semiconductor field-effect-transistor (MOSFET) device electrically attachable to a first data line and a read-only memory (ROM) element. The ROM element is electrically interposable between the MOSFET device and a second data line. The ROM element includes first and second sets of memory cells in high and low resistance states, respectively, to form a secure identifier (ID).

Read-only memory for chip security that is MOSFET process compatible

Growing community of inventors

Schenectady, NY, United States of America

Tenko Yamashita