Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Uwiz Technology Co., Ltd.

United Microelectric Corp.

Teng-Chun Tsai

Shen-Nan Lee

Li-Ting Wang

Cheng-Tung Lin

Kuo-Yin Lin

Chen-Hao Wu

De-Fang Chen

Neng-Kuo Chen

Yung-Cheng Lu

Huan-Just Lin

Chun-Yuan Wu

Chih-Chien Liu

Chin-Cheng Chien

Chin-Fu Lin

Huang-Lin Chao

Chia-Lin Hsu

Chun-Hung Liao

Chi-Yuan Chen

Chien-Chung Huang

Fu-Ting Yen

Chung-Wei Hsu

Chih-Tang Peng

Huang-Yi Huang

Zhi-Chang Lin

Chang-Sheng Lin

Huicheng Chang

Chia-Jung Hsu

Chien-Hsun Wang

Tsu-Hsiu Perng

Yasutoshi Okuno

Wei-Hao Wu

Hong-Mao Lee

Wei-Jung Lin

Hui-Cheng Chang

Chin-Hsiang Lin

Yi-Wei Chen

Keng-Chu Lin

Ming-Ching Chang

Chun-Hung Lee

Mrunal Abhijith Khaderbad

Chia-Wei Su

Hsiang-Pi Chang

Po-Cheng Huang

Chih-Hao Wang

Feng-Cheng Yang

Ming-Sheng Yang

Kai-Chieh Yang

Shwang-Ming Jeng

Po-Yu Lin

Tzu-Hsiang Hsu

Kuan-Lun Cheng

Kuo-Cheng Ching

Hsueh-Chung Chen

Tai-Chun Huang

Chien-Ting Lin

Ming-Hsing Tsai

Chun-Hsiung Lin

Wen-Han Hung

Hung-Ta Lin

Chih-Chang Hung

Yee-Chia Yeo

Kuo-Cheng Chiang

Tze-Liang Lee

Ziwei Fang

Sung-Li Wang

Pang-Yen Tsai

Kuo-Chih Lai

Hsin-Hsien Lu

Gin-Chen Huang

Tien-I Bao

Yen-Yu Chen

Shi Ning Ju

Shyh-Fann Ting

Chan-Lon Yang

Shih-Hung Tsai

Ying-Ho Chen

Cheng-Tung Huang

Shuen-Shin Liang

Wen-Yi Hsieh

Tzyy-Ming Cheng

Nien-Ting Ho

Kun-Hsien Lee

Ding-Kang Shih

Ying-Tsung Chen

Chun-I Tsai

Chen-Han Wang

Ching-Wei Tsai

Chun-Hsien Lin

Jiunn-Hsiung Liao

Ching-Feng Fu

Ming-Chyi Liu

Hsin-Fu Huang

Shui-Yen Lu

Zhi-Cheng Lee

Che-Hua Hsu

Pei-Yu Chou

Min-Chuan Tsai

Yi-Wen Chen

Yen-Chun Huang

Joy Cheng

A CMP slurry composition and a method of polishing a metal layer are provided. In some embodiments, the CMP slurry composition includes about 0.1 to 10 parts by weight of a metal oxide, and about 0.1 to 10 parts by weight of a chelator. The chelator includes a thiol compound or a thiolether compound.

Chemical mechanical polishing slurry composition and method of polishing metal layer

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate; a first conductive feature and a second conductive feature disposed on the semiconductor substrate; and a staggered dielectric feature interposed between the first and second conductive feature. The staggered dielectric feature includes first dielectric layers and second dielectric layers being interdigitated. The first dielectric layers include a first dielectric material and the second dielectric layers include a second dielectric material being different from the first dielectric material.

Semiconductor structure with staggered selective growth

A semiconductor device and a method of forming the same are provided. A method includes forming a gate over a semiconductor structure. An epitaxial source/drain region is formed adjacent the gate. A dielectric layer is formed over the epitaxial source/drain region. An opening extending through the dielectric layer and exposing the epitaxial source/drain region is formed. A conductive material is non-conformally deposited in the opening. The conductive material fills the opening in a bottom-up manner.

Contact plugs for semiconductor device and method of forming same

Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium.

Partial barrier free vias for cobalt-based interconnects and methods of fabrication thereof

The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers.

Spacer structure for semiconductor device

According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

Vertical device having a protrusion source

The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.

Integrated circuit with a Fin and gate structure and method making the same

A method disclosed herein includes forming a polishing pad configured for a chemical-mechanical polishing (CMP) process and polishing a workpiece using the polishing pad and a CMP slurry. Forming the polishing pad includes forming an interpenetrating polymer network having a first phase and a second phase embedded in the first phase, removing the second phase from the interpenetrating polymer network, thereby forming a porous top pad that includes a network of pores embedded in the first phase, and adhering the porous top pad to a sub pad, thereby forming the polishing pad. The second phase is different from the first phase in composition, and the interpenetrating polymer network has a substantially periodic pattern. Surface roughness of the porous top pad is consistent during the polishing of the workpiece.

Fabrication of a polishing pad for chemical mechanical polishing

The method includes receiving a semiconductor device having a first surface and a second surface. The first surface is a top surface including a conductive material exposed thereon; and the second surface is an embedded surface including the conductive material and a dielectric material. The method also includes selecting a first polishing slurry to achieve a first polishing rate of the conductive material in the first polishing slurry and a second polishing rate of the dielectric material in the first polishing slurry. The method further includes selecting a second polishing slurry to achieve a third polishing rate of the conductive material in the second polishing slurry and a fourth polishing rate of the dielectric material in the second polishing slurry. The method additionally includes polishing the first surface with the first polishing slurry until the second surface is exposed; and polishing the second surface with the second polishing slurry.

Slurry compositions for chemical mechanical planarization

The present disclosure provides a method for manufacturing a semiconductor. The method includes: forming a metal oxide layer over a gate structure over a substrate; forming a dielectric layer over the metal oxide layer; forming a metal layer over the metal oxide layer; and performing a chemical mechanical polish (CMP) operation to remove a portion of the dielectric layer and a portion of the metal layer, the CMP operation stopping at the metal oxide layer, wherein a slurry used in the CMP operation includes a ceria compound. The present disclosure also provides a method for planarizing a metal-dielectric surface.

Method for manufacturing a semiconductor using slurry

An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

Dummy fin structures and methods of forming same

Examples of a technique for forming a dielectric material for an integrated circuit are provided herein. In an example, an integrated circuit workpiece is received that includes a recess. A first dielectric precursor is deposited in the recess. The first dielectric precursor includes a non-semiconductor component. A second dielectric precursor is deposited in the recess on the first dielectric precursor, and an annealing process is performed such that a portion of the non-semiconductor component of the first dielectric precursor diffuses into the second dielectric precursor. The non-semiconductor component may include oxygen, and the annealing process may be performed in one of a vacuum or an inert gas environment.

Integrated circuit isolation feature and method of forming the same

The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.

Capping layer for gate electrodes

Growing community of inventors

Hsinchu, Taiwan

Teng-Chun Tsai