Macronix International Co., Ltd.

Ten Hao Yeh

Wenpin Lu

Ming Shang Chen

Tzung Ting Han

Shih Chin Lee

Shaw Hung Ku

Chia Wei Wu

Shang Wei Lin

A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

Flash memory having insulating liners between source/drain lines and channels

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Hsinchu, Taiwan

Ten Hao Yeh