Microsoft Technology Licensing, LLC

Ten H Tzen

Patrick W Sathyanathan

Terry Jack Mahaffey

Wenlei He

Arun Upadhyaya Kishan

Ankit Asthana

Pedro Miguel Sequeira De Justo Teixeira

Youssef M Barakat

Hakki Tunc Bostanci

Henry Morgan

Kalpesh S Patel

YongKang Zhu

Michael Trevor Pashniak

Olaf Alexander Miller

Christopher Martin McKinsey

Shishir Sharma

Todd Edward Sharpe

Adrian Militaru

Pratap Chandar Joseph

Shukang Zhou

Changqing (Charles) Fu

Ayman Baligh Shoukry

Changqing Fu

Pratap Joseph Chandar

In order to reduce the number of instructions that the compiler generates to load the address of a global variable into a register, the compiler uses a technique that analyzes the global variables used in each function in order to estimate which global variables will be located within the same memory page and have a common base address. A base global variable is selected for each function whose address is fully resolved. The address of each subsequent global variable is constructed using an offset relative to the address of the base global variable that is based on the subsequent global variable's position in a global variable order list.

Reduced instructions to generate global variable addresses

During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint. If so, the emulator emits machine code instruction(s) in the second ISA that perform the memory operation using a memory barrier.

Memory ordering annotations for binary emulation

In order to reduce the number of instructions that the compiler generates to load the address of a global variable into a register, the compiler uses a technique that analyzes the global variables used in each function in order to estimate which global variables will be located within the same memory page and having a common base address. A base global variable is selected for each function whose address is fully resolved. The address of each subsequent global variable is constructed using an offset relative to the address of the base global variable that is based on the subsequent global variable's position in a global variable order list.

A profile guided optimization compiler utilizes sample profile data including a control flow representation of a program having block counts associated with each basic block of the program, and edge counts associated with each control flow edge estimated from the block counts. The sample profile data utilizes correlation data to map the address of a sampled instruction from a fully optimized binary directly into a corresponding basic block of source code control flow of the program using a relative virtual address (RVA) that is associated with each source code basic block and the sampled instruction. The correlation data is able to differentiate multiple blocks on the same source code line and handle inlining and optimizations with greater precision and efficiency. The block counts are then used to guide the optimization of the program.

Sample driven profile guided optimization with precise correlation

One embodiment illustrated herein includes a method that may be practiced in a computing environment with a guest architecture running a native architecture system. The method includes acts for handling function calls. The method includes receiving a call to a hybrid binary, wherein the call is in a format for the guest architecture. The hybrid binary includes a native function compiled into a native architecture binary code using guest architecture source code, an interoperability thunk to handle an incompatibility between the guest architecture and the native architecture, and native host remapping metadata that is usable by an emulator to redirect native host callable targets to the interoperability thunk. The method further includes invoking the interoperability thunk to allow the native function in the hybrid binary to be executed natively on the native architecture system.

Performance optimizations for emulators

Systems and methods for the mitigation of return-oriented programming are disclosed. A return address for a function is encrypted to generate an encrypted return address. The encrypted return address is stored as the return address for the function. The encrypted return address can be decrypted prior to a return instruction of the function.

Return-oriented programming mitigation

Methods, systems, and computer program products are provided that enable incremental compilation of source code. Attributes of an intermediate language (IL) representation and a compiled representation of a source code are stored. Modified source code that is a revised version of the first source code is received. An IL representation of the modified source code is generated. Attributes of the revised intermediate IL and the stored attributes of the IL representation are compared to determine a first set of functions changed in the modified source code. A second set of functions in the first source code is determined that includes functions affected the determined first set of functions. The first and second sets of functions are compiled to generate a set of compiled functions. Compiled versions of the first and second sets are replaced in the compiled representation of the first source code with the set of compiled functions.

Incremental whole program compilation of code

One embodiment illustrated herein includes a method that may be practiced in a computing environment with a guest architecture running a native architecture system. The method includes acts for handling function calls. The method includes receiving a call to a target binary, wherein the call is in a format for the guest architecture. The method further includes determining that the call is to a binary that is a hybrid binary. The hybrid binary includes a native function compiled into a native architecture binary code using guest architecture source code and a specialized thunk to handle an incompatibility between the guest architecture and the native architecture. The method further includes invoking the specialized thunk to allow the native function in the hybrid binary to be executed natively on the native architecture system.

Methods, systems, and computer program products are provided that enable a portion of code to be marked in source code to disable compilation optimizations for the marked portion of code, while the rest of the source code is compiled with optimizations. In this manner, edit-and-continue debugging may be performed on the compiled source code in an enhanced manner. Modifications made to the marked source code (as well as the rest of the source code) may be compiled in an incremental manner, such that the portions of the source code affected by the modifications are compiled, while unaffected portions of the source code are not recompiled.

Techniques for edit-and-continue and enhanced optimized debugging on optimized code

Multiphased profile guided optimization optimizes executable code based on data collected during multiple training runs of a training executable. In multiphased profile guided optimization, multiple sets of profiling data are collected where each set of profiling data is associated with a program phase and a particular training run. Program phases include but are not limited to different program features, startup, steady state and shutdown. The program features can run concurrently. Priority of the phases can be specified.

Multiphased profile guided optimization

Instead of performing local dataflow analyses on all procedures during a multi-file optimized code generation, those dataflow analyses are done only on a generally much smaller set of procedures that were actually impacted by source code edits. Incremental inter-procedural dataflow analysis (IIPDA) code identifies a set of procedures to be recompiled due to impact from one or more edits and does local dataflow analyses only on them. Results of the incremental approach for use in generating optimized code match the results of a more expensive exhaustive interprocedural dataflow analysis of all procedures, even when call graph structure has been changed by the edits. The impacted procedures are identified based on which procedures were edited, dataflow values, intermediate language representations, and a portion of the call graph.

Incremental interprocedural dataflow analysis during compilation

Compiler based obfuscation is described. To protect portions of a code project with obfuscations, the code is modified within a compiler to produce one or more modifications that obfuscate the code as part of a compilation process. A compiled version of the code is generated having the modifications that are produced within the compiler. In one approach, the compiler is configured to consume an obfuscation description that indicates portions of the code to protect and specifies the modifications to make to the indicated portions. Various different modifications of code may be performed during the compilation process to implement corresponding obfuscation features. For example, the modifications made within a compiler may include, but are not limited to, modifications designed to enable tamper detection, anti-debugging, and/or encryption of the code.

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Redmond, WA, United States of America

Ten H Tzen