Intel Corporation

Telesphor Kamgaing

Georgios C Dogiamis

Johanna M Swan

Adel A Elsherbini

Aleksandar Aleksov

Sasha N Oster

Feras Eid

Henning Braunisch

Vijay K Nair

Valluri Ramana Rao

Shawna M Liff

Brandon M Rawlings

Richard J Dischler

Neelam Prabhu Gaunkar

Diego Correas-Serrano

Hyung-Jin Lee

Kristof Darmawikarta

Veronica Aleman Strong

Emanuel Cohen

Erich Nolan Ewy

Gilbert W Dewey

Fay Hua

Robert L Sankman

Ofir Degani

Yoshihiro Tomita

Javier A Falcon

Uwe Zillmann

Bradley Oraw

Andreas Duevel

Srinivas V Pietambaram

Kemal Aygun

Sri Ranga Sai Boyapati

Emile Davies-Venn

Robert Alan May

Rahul Khanna

Mathew J Manusharow

William J Lambert

Stefano Pellerano

Eyal Fayneh

Krishna Bharath

Javier Soto Gonzalez

Ruchir Saraswat

Kenneth D Shoemaker

Suddhasattwa Nad

Gaurav Chawla

Andre Schaefer

Ping Ping Ooi

Meizi Jiao

Sarah Kay Haney

Baris Bicen

Chang-Tsung Fu

Chan Kim Lee

David Levy

Abhishek A Sharma

Thorsten Meyer

Bernhard Raaf

Paul B Fischer

Omkar G Karhade

Rahul N Manepalli

John Stephen Guzek

Min Suet Lim

Zhiguo Qian

Eng Huat Goh

Khang Choong Yong

Eric Jin Li

Wilfred Gomes

Kyu Oh Lee

James Chris Matayabas, Jr

Rahul Jain

Weng Hong Teh

Harish Krishnamurthy

Ravi V Mahajan

Georgios Yorgos Palaskas

Sai Vadlamani

Tarek A Ibrahim

Wil Choon Song

Jeff C Morriss

Boon Ping Koh

Daniel N Sobieski

Charles A Gealer

Pablo Herrero

Cho-Ying Lu

Chintan S Thakkar

Jiwei Sun

Benjamin Duong

Ajay Balankutty

Torrey W Frank

Guido Droege

Pascal A Meier

Parshuram Balkrishna Zantye

Yorgos Palaskas

Chung Peng Jackson Kong

Timothy E McIntosh

Said Rami

Uwe Zillman

Chad E Mair

Thomas W Brown

Cooper S Levy

Adewale K Oladeinde

Chung Peng (Jackson) Kong

Embodiments disclosed herein include package substrates and methods of fabricating such substrates. In an embodiment, a package substrate comprises a core with a first surface and a second surface opposite from the first surface. The package substrate further comprises a via hole through the core. In an embodiment the via hole comprises a first portion, a second portion, and a perforated ledge between the first portion and the second portion. In an embodiment, the package substrate further comprises a via filling the via hole.

Physical vapor deposition seeding for high aspect ratio vias in glass core technology

Embodiments disclosed herein include coplanar waveguides and methods of forming coplanar waveguides. In an embodiment, a coplanar waveguide comprises a core, and a signal trace on the core. In an embodiment, the signal trace has a first edge and a second edge. In an embodiment, a first ground trace is over the core, and the first ground trace is adjacent to the first edge of the signal trace. In an embodiment, a first ground via plane is below the first ground trace. The coplanar waveguide may further comprise a second ground trace over the core, and the second ground trace is adjacent to the second edge of the signal trace. In an embodiment, a second ground via plane below the second ground trace.

Compact surface transmission line waveguides with vertical ground planes

Embodiments disclosed herein include package substrates with filter architectures. In an embodiment, a package substrate comprises a core with a first surface and a second surface, and a filter embedded in the core. In an embodiment, the filter comprises a ground plane, where the ground plane is substantially orthogonal to the first surface of the core, and a resonator adjacent to the ground plane.

RF filters and multiplexers manufactured in the core of a package substrate using glass core technology

Embodiments of the present disclosure are based on using transistors with back-side contacts. Such transistors enable back-side power delivery to IC components (e.g., transistors, etc.) of an IC structure, which may be more advantageous than front-side power delivery in some implementations. Embodiments of the present disclosure are further based on recognition that using a glass support structure at the front side of an IC structure with back-side power delivery may advantageously reduce parasitic effects in the IC structure, e.g., compared to using a silicon-based support structure at the front.

Back-side power delivery with glass support at the front

Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a substrate with a first surface and a second surface, where the substrate comprises glass. In an embodiment, the electronic package further comprises a via opening through the substrate, where sidewalls of the via opening have a root mean squared (RMS) surface roughness that is approximately 100 nm or greater. In an embodiment, the electronic package further comprises a liner over the sidewalls of the via opening, where an RMS surface roughness of the liner is approximately 50 nm or smaller. An electronic package may further comprise a via through the via opening.

Dielectric film coating for through glass vias and plane surface roughness mitigation

Embodiments disclosed herein include package substrates and methods of forming such package substrates. In an embodiment the package substrate comprises a core and buildup layers on the core. In an embodiment, first level interconnect (FLI) pads are on a topmost buildup layer, and the FLI pads have a pitch. In an embodiment, a plurality of vertically oriented planes are embedded in the core, and the vertically oriented planes are spaced at the pitch.

Package substrate with glass core having vertical power planes for improved power delivery

In various embodiments, disclosed herein are systems and methods directed to the fabrication of a coreless semiconductor package (e.g., a millimeter (mm)-wave antenna package) having an asymmetric build-up layer count that can be fabricated on both sides of a temporary substrate (e.g., a core). The asymmetric build-up layer count can reduce the overall layer count in the fabrication of the semiconductor package and can therefore contribute to fabrication cost reduction. In further embodiments, the semiconductor package (e.g., a millimeter (mm)-wave antenna packages) can further comprise dummification elements disposed near one or more antenna layers. Further, the dummification elements disposed near one or more antenna layers can reduce image current and thereby increasing the antenna gain and efficiency.

Semiconductor packages with antennas

Glass substrates having signal shielding for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a core layer defining a channel and a through glass via (TGV). The channel at least partially surrounding the TGV. A signal transmission line is provided in the opening and extending through the core layer. An electrically conductive material positioned in the channel. The conductive material to provide electromagnetic shielding to the transmission line.

Glass substrates having signal shielding for use with semiconductor packages and related methods

Embodiments disclosed herein include electronic packages with magnetic features and methods of forming such packages. In an embodiment, a package substrate comprises a core and a conductive via through a thickness of the core. In an embodiment, a shell surrounds a perimeter of the conductive via and the shell is a magnetic material. In an embodiment, a surface of the conductive via is spaced away from the shell.

Magnetic planar spiral and high aspect ratio inductors for power delivery in the glass-core of a package substrate

Embodiments described herein may be related to apparatuses, processes, and techniques related to via structures and/or planar structures within a glass core of a substrate to facilitate high-speed signaling with a die coupled with the substrate. In embodiments, the substrate may be coupled with an interposer to enable high-speed signaling between a compute die (or tile) and a storage die (or tile) that may be remote to the substrate. Other embodiments may be described and/or claimed.

Die coupling using a substrate with a glass core

Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.

Thermal management in integrated circuit packages

Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.

Components for millimeter-wave communication

Embodiments described herein may be related to apparatuses, processes, and techniques related to a transceiver architecture for inter-die communication on-package using mm-wave/THz interconnects. In particular, amplifier-less transceivers are used in combination with on-package low loss transmission lines to provide inter-die communication. In embodiments, signals on the interconnect may be transmitted between up conversion mixers and down conversion mixers without any additional amplification. Other embodiments may be described and/or claimed.

Die to die high-speed communication without discrete amplifiers between a mixer and transmission line

A method of forming a waveguide comprises forming an elongate waveguide core including a dielectric material; and arranging a conductive sheet around an outside surface of the dielectric core to produce a conductive layer around the waveguide core.

Methods for conductively coating millimeter waveguides

Growing community of inventors

Chandler, AZ, United States of America

Telesphor Kamgaing