Xilinx, Inc.

Tejus Siddagangaiah

Elliott Delaye

Aaron Ng

Ehsan Ghasemi

Xiao Teng

Satyaprakash Pareek

Rajeev Patwari

Jorn Tuyls

Hyun Kwon

Sanket Pandit

Andrew Gozillon

Bryan Lozano

Ronan Keryell

Pramod Peethambaran

Controlling a data processing (DP) array includes creating a replica of a register address space of the DP array based on the design and the DP array. A sequence of instructions, including write instructions and read instructions, is received. The write instructions correspond to buffer descriptors specifying runtime data movements for a design for a DP array. The write instructions are converted into transaction instructions and the read instructions are converted into wait instructions based on the replica of the register address space. The transaction instructions and the wait instructions are included in an instruction buffer. The instruction buffer is provided to a microcontroller configured to execute the transaction instructions and the wait instructions to implement the runtime data movements for the design as implemented in the DP array. In another aspect, the instruction buffer is stored in a file for subsequent execution by the microcontroller.

Instruction set architecture for data processing array control

Examples herein describe compiling source code for a heterogeneous computing system that contains jump logic for executing multiple accelerator functions. The jump logic instructs the accelerator to execute different functions without the overhead of reconfiguring the accelerator by, e.g., providing a new configuration bitstream to the accelerator. At start up when a host program is first executed, the host configures the accelerator to perform the different functions. The methods or system calls in the host program corresponding to the different functions then use jump logic to pass function selection values to an accelerator program in the accelerator that inform the accelerator program which function it is being instructed to perform. This jump logic can be generated by an accelerator compiler and then inserted into the host program as a host compiler generates the executable (e.g., the compiled binary) for the host program.

Performing multiple functions in single accelerator program without reload overhead in heterogenous computing system

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San José, CA, United States of America

Tejus Siddagangaiah