Stmicroelectronics International N.v.

Xilinx, Inc.

Tejinder Kumar

Rakesh Malik

Akshat Jain

Surender Reddy Kisanagar

Rathod Ronak Kishorbhai

Suchi Prabhu Tandel

Apurva Sen

A device includes a first and a second stage round robin arbitrations receiving request signals associated with a first, a second and a third user. At least one request signal for each of the first, the second, and the third user is asserted to access a common resource. The first stage round robin arbitration selects the first, the second, and the third user in a round robin fashion, at a first, a second, and a third iteration. The second stage round robin arbitration receives the user selection and the plurality of request signals and at the first, the second, and the third iteration grants access to the common resource to one request signal associated with the first, the second, and the third user. At each subsequent iteration the first stage round robin arbitration selects a different user and grants access to another request signal until all request signals are processed.

Multistage round robin arbitration in a multiuser system

A device includes a first and a second stage round robin arbitrations. The first stage receives request signals and selects a subset the request signals. Each request signal is associated with whether a component is requesting access to a common resource. The second stage receives the selected subset and grants access to the common resource to each request signal of the selected subset that is requesting access, in a round robin fashion. The second stage outputs an enable signal to the first stage when the selected subset is processed. The first stage selects another subset and transmits the selected another subset to the second stage for round robin processing thereof. The process is repeated until all subsets with at least one request signal to access the common resource is processed and granted access in a round robin fashion.

Multistage round robin arbitration

Various embodiments provide a content addressable memory (CAM) architecture that utilizes non-bit addressable memory, such as a single or dual port random access memory. The CAM includes a first non-bit addressable memory, a second non-bit addressable memory, a multiplexer, a write operation encoder, a read operation encoder, and a match signal generator. In contrast to bit addressable memories, non-bit addressable memories are widely available, have high performance frequency, and are area efficient as compared to bit addressable memories. Accordingly, the CAM architecture described herein has low costs and time to market, increased processing time, and improved area efficiency.

High operation frequency, area efficient and cost effective content addressable memory architecture

CRC generation circuitry includes a lookup-table storing N-bit CRC values for M one-hot data frames. N AND gates for each bit of a M-bit data frame receive that bit of the M-bit data frame and a different bit of a N-bit CRC value from the lookup-table corresponding to a position of the bit in the M-bit data frame. N exclusive-OR gates each receive output from one of the N AND gates for each bit of the M-bit data frame. The N exclusive-OR gates generate a final N-bit CRC value for the M-bit data frame. The CRC value is therefore generated with a purely combinational circuit, without clock cycle latency. Area consumption is small due to the small lookup-table, which itself permits use of any generator polynomial, and is independent of the width of the received data frame. This device can also generate a combined CRC for multiple frames.

Parallel pipeline logic circuit for generating CRC values utilizing lookup table

Various embodiments provide a parallel checker to determine whether a device under test (DUT) is functioning properly or outputting erroneous bits. A test pattern or test data is injected into the DUT, and the parallel checker compares output data of the DUT to expected data stored in the parallel checker. The parallel checker determines an error in the event that a bit in the output data does not match in the expected data. The parallel checker is independent of test pattern length and data width at the parallel input of the parallel checker. Accordingly, the parallel checker may be used for multiple different test patterns, such as a PRBS 7, a CJTPAT, CRPAT, etc. Further, the parallel checker provides high-speed synchronization between data received from the DUT and expected test data stored in the parallel checker. In addition, the parallel checker consumes relatively low power and chip area in, for example, a SoC environment.

Low area parallel checker for multiple test patterns

Disclosed herein is a test circuit for testing a device under test (DUT). The test circuit receives a test pattern output by the DUT. A content addressable memory (CAM) stores expected test data at a plurality of address locations, receives the test pattern, and outputs an address of the CAM containing expected test data matching the received test pattern. A memory also stores the expected test data at address locations corresponding to the address locations of the CAM. A control circuit causes the memory to output the expected test data stored therein at the address output by the CAM. Comparison circuitry receives the test pattern from the input, and compares that received test pattern to the expected test data output by the control circuit, and generates an error count as a function of a number of bit mismatches between the received test pattern and the expected test data.

Generic width independent parallel checker for a device under test

Disclosed herein is a test apparatus for a device under test. The test apparatus includes a voltage translator coupled to receive test data from the device under test, over a physical interface, using one of a plurality of I/O standards, with the voltage translator being capable of communication using each of the plurality of I/O standards. A programmable interface is configured to receive the test data from the voltage translator. A bit error rate determination circuit is configured to receive the test data from the programmable interface and to determine a bit error rate of reception of the test data over the physical interface based upon a comparison of the test data to check data.

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Moga, India

Tejinder Kumar