Intel Corporation

Tahoe Research, Ltd.

Tejaswi K Indukuri

Ramanan Chebiam

James S Clarke

Christopher J Jezewski

Hui Jae Yoo

Colin T Carver

Flavio Griggio

Ruth Amy Brain

Yuriy V Shusterman

Kevin O'Brien

Brian S Doyle

Mark L Doczy

Kaan Oguz

Charles C Kuo

Florian Gstrein

Satyarth Suri

John J Plombon

Ravi Pillarisetty

Niloy Mukherjee

Uday Shah

Prashant Majhi

Elijah V Karpov

Kanwal Jit Singh

Daniel B Bergstrom

Kevin P O'brien

Srijit Mukherjee

Arnel M Fajardo

Rohan N Akolkar

Daniel J Zierath

Alan M Meyers

Ramanan V Chebiam

An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.

Cobalt based interconnects and methods of fabrication thereof

A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

Interconnect wires including relatively low resistivity cores

A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity &#x3c1;1 and the core material exhibits a second resistivity &#x3c1;2 and &#x3c1;2 is less than &#x3c1;1.

In one embodiment, a conductive connector for a microelectronic component may be formed with a noble metal layer, acting as an adhesion/wetting layer, disposed between a barrier liner and a conductive fill material. In a further embodiment, the conductive connector may have a noble metal conductive fill material disposed directly on the barrier liner. The use of a noble metal as an adhesion/wetting layer or as a conductive fill material may improve gapfill and adhesion, which may result in the conductive connector being substantially free of voids, thereby improving the electrical performance of the conductive connector relative to conductive connectors without a noble metal as the adhesion/wetting layer or the conductive fill material.

Use of noble metals in the formation of conductive connectors

Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.

Decoupled via fill

Embodiments of the present invention include RRAM devices and their methods of fabrication. In an embodiment, a resistive random access memory (RRAM) cell includes a conductive interconnect disposed in a dielectric layer above a substrate. An RRAM device is coupled to the conductive interconnect. An RRAM memory includes a bottom electrode disposed above the conductive interconnect and on a portion of the dielectric layer. A conductive layer is formed on the bottom electrode layer. The conductive layer is separate and distinct from the bottom electrode layer. The conductive layer further includes a material that is different from the bottom electrode layer. A switching layer is formed on the conductive layer. An oxygen exchange layer is formed on the switching layer and a top electrode is formed on the oxygen exchange layer.

RRAM devices and their methods of fabrication

Embodiments of the present disclosure describe removing seams and voids in metal interconnects and associated techniques and configurations. In one embodiment, a method includes conformally depositing a metal into a recess disposed in a dielectric material to form an interconnect, wherein conformally depositing the metal creates a seam or void in the deposited metal within or directly adjacent to the recess and heating the metal in the presence of a reactive gas to remove the seam or void, wherein the metal has a melting point that is greater than a melting point of copper. Other embodiments may be described and/or claimed.

Seam healing of metal interconnects

Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for removing a re-deposited layer and/or interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.

Spin transfer torque memory (STTM), methods of forming the same using volatile compound forming elements, and devices including the same

Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.

Spin transfer torque memory (STTM), methods of forming the same using a non-conformal insulator, and devices including the same

Growing community of inventors

Portland, OR, United States of America

Tejaswi K Indukuri