Xilinx, Inc.

Teja Masina

Santosh Yachareni

Shidong Zhou

Kumar Rahul

Jing Jing Chen

Narendra Kumar Pulipati

Sree Rkc Saraswatula

Md Nadeem Iqbal

Sourabh Swarnkar

Suresh Babu Kotha

Jitendra Kumar Yadav

A circuit includes a master latch circuit and a slave latch circuit. The master latch circuit is configured to receive an input data signal associated with an input data voltage domain and generate a first output data signal associated with an output data voltage domain different from the input data voltage domain. The slave latch circuit is configured to receive, from the master latch circuit, the first output data signal and generate a second output data associated with the output data voltage domain.

Method and apparatus for multi-voltage domain sequential elements

An example read address generation circuit for a static random access memory (SRAM) cell includes an operational amplifier having a non-inverting input coupled to a reference voltage, a memory emulation circuit having an output coupled to an inverting input of the operational amplifier and a control input coupled to an output of the operational amplifier, and a multiplexer having a first input coupled to receive a constant read voltage, a second input coupled to the output of the operational amplifier, and an output coupled to supply a read address voltage to the SRAM cell.

Adaptive read scheme for configuration SRAMs in a programmable device

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Hyderabad Telangana, India

Teja Masina