Altera Corporation

Intel Corporation

Teik Wah Lim

Ashraf W Lotfi

Boon Jin Ang

Thow Pang Chong

Eng Huat Lee

Kim Pin Tan

Ie Chen Chia

John David Weld

Chooi Pei Lim

Choong Kit Wong

Ket Chiew Sia

Boon Haw Ooi

Keong Hong Oh

Woi Jie Hooi

The disclosure relates to systems and methods for sector-to-sector and die-to-die clock synchronization in programmable logic devices. The methods and systems may employ phase difference detector and programmable delay elements to minimize skews in the clock tree and facilitate timing closure of time-critical paths and increase in operating frequencies.

Clock synchronization in multi-die field programmable gate array devices

A voltage regulator package includes a voltage regulator module that outputs a voltage signal of a particular voltage level through an output terminal is provided. The voltage regulator module may be switched on according to a periodic signal having a periodic signal frequency as a variable. The periodic signal frequency may be tuned to reduce impedance, jitter, or noise.

Voltage regulator with jitter control

A packaged integrated circuit and method of forming the same. The package integrated circuit includes an integrated circuit formed on a semiconductor die affixed to a surface of a multi-layer substrate, and a switch-mode regulator formed on the semiconductor die (or another semiconductor die) affixed to the surface of the multi-layer substrate. The integrated circuit and the switch-mode regulator are integrated within a package to form the packaged integrated circuit.

Packaged integrated circuit including a switch-mode regulator and method of forming the same

Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.

Frequency control clock tuning circuitry

A circuit and methods for placing a circuit block on an integrated circuit (IC) are disclosed. An embodiment of the disclosed method includes dividing the IC into multiple regions based on pre-determined value. This pre-determined value may be a voltage drop value measured on specific regions on the IC. The performance requirement for the circuit block is determined and placed in one of the regions on the IC. In one embodiment, the placement of the circuit block is based on the performance requirement and the measured value at specific regions on the IC. The measured value may be a voltage drop value and a circuit block with a higher performance may be placed in a region with a lower voltage drop value.

Voltage drop aware circuit placement

Growing community of inventors

Bayan Lepas, Malaysia

Teik Wah Lim