Altera Corporation

Teik Tiong Toong

Loon Kwang Tan

Chooi Pei Lim

Jordan Plofsky

Yee Liang Tan

Ken Beng Lim

Chong Poh Lim

A multi-package unit having stacked packages is provided. A multi-package unit may include a first package and a second package mounted on the first package. The first package may be a leadframe package that includes metal leads extending beyond the perimeter of the first package. The first package may include a first integrated circuit die assembled within the first package using the wirebond configuration or the flip-chip configuration. The second package may be a leadframe package or a leadless package that includes a second integrated circuit die. The second package may be smaller than the first package. The first and second integrated circuit dies may be formed using different integrated circuit fabrication technologies.

Stacked leadframe packages

An integrated circuit (IC) package that includes a lead frame, and a die affixed to a first surface of a pad of the lead frame. The die is wire bonded to the lead frame. The package includes a heat sink spaced apart from a second surface of the pad, where the second surface opposes the first surface. Molding compound encapsulates the lead frame and the die. The molding compound is disposed between the heat sink and the second surface of the pad and is enabled access between the heat sink and the second surface through protruding features disposed on the heat sink, the second surface, and/or some combination of the two.

Package having spaced apart heat sink

Systems including an input/output (I/O) stack and methods for fabricating such systems are described. In one implementation, the methods include stacking an I/O die including I/O elements and excluding a logic element. Also in one implementation, the methods further include stacking an integrated circuit die with respect to the I/O die. The integrated circuit includes logic elements and excludes an I/O element. The separation of the I/O die from the integrated circuit die provides various benefits, such as independent development of each of the dies and more space for the I/O elements on an I/O substrate of the I/O die compared to that in a conventional die. The increase in space allows new process generation of the integrated circuit die in which an increasing number of logic elements are fitted within the same surface area of a substrate of the integrated circuit die.

Systems including an I/O stack and methods for fabricating such systems

In an exemplary embodiment, a method takes as an input a package substrate on which multiple capacitors have been mounted in a ring as part of a design to effectuate on-package decoupling. The method involves plasma cleaning the package substrate and the capacitors to remove organic contaminants. The method then involves applying a thermoset plastic to encase the capacitors on the package substrate. In one embodiment, a heated metal mold is utilized and the thermoset plastic is placed therein. The method includes opening the metal mold and curing the molded thermoset plastic by baking the molded thermoset plastic at an elevated temperature.

Thermoset molding for on-package decoupling in flip chips

An integrated circuit (IC) package with a plurality of chip capacitors placed on a surface of a die is disclosed. The chip capacitors may be placed on top of the die with an interposal substrate layer. Placing chip capacitors on top of the die may reduce the size of the packaging substrate required. One or more wires may be used to connect the chip capacitors on the interposal layer to the packaging substrate. The IC package may include a lid and a thermal interface material (TIM) placed on top of the die. The lid may be shaped such that a protruding portion of the lid contacts the die directly through the TIM to improve heat dissipation.

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Simpang Ampat, Malaysia

Teik Tiong Toong