Advanced Micro Devices Corporation

Samsung Electronics Co., Ltd.

Texas Instruments Corporation

Teik-Chung Tan

Benjamin T Sander

Brian D McMinn

Kelvin Domnic Goveas

Michael E Tuuk

Wing-Shek Wong

Thang M Tran

William Alexander Hughes

Derrick R Meyer

Mitchell K Alsup

Jerry D Moench

Bradley Gene Burgess

Gregory William Smaus

Sridhar P Subramanian

Stephen Charles Kromer

Matthew M Crum

Ravi Iyengar

Joe Peters

Adam Duley

A method and apparatus for register packing prior to register renaming in a microprocessor are provided. The method includes: receiving a plurality of micro operations (micro-ops) decoded from one or more instructions; packing a plurality of registers which are included in the micro-ops into a packed register structure including a plurality of packed registers based on a preset number of rename ports of a renamer through which the packed registers are read or written for register renaming; and sending the packed registers for register renaming.

Micro-ops including packed source and destination fields

For a memory access at a processor, only a subset (less than all) of the ways of a cache associated with a memory address is prepared for access. The subset of ways is selected based on stored information indicating, for each memory access, which corresponding way of the cache was accessed. The subset of ways is selected and preparation of the subset of ways is initiated prior to the final determination as to which individual cache way in the subset is to be accessed.

Way preparation for accessing a cache

A method and circuit for fast flag generation. The circuit is coupled to receive data to be shifted, the data including a first plurality of bits. A shift count value (including a second plurality of bits) is also received by the circuit, as well as an indication of a direction the data is to be shifted. Based on the shift count value and the indication of direction, the position of a bit within the data is determined. The bit is then output as a flag bit.

Fast flag generation

Various embodiments of methods and systems for storing multiple groups of microcode operations and corresponding control sequences per row of microcode ROM are disclosed. In one embodiment, an integrated circuit may include a microcode ROM coupled to a control sequence logic unit. The microcode ROM may store multiple groups of microcode operations per row. For each group of microcode operations stored in a row, a corresponding control sequence may also be stored in the row. Each group of microcode operations may be included in a microcode routine. The groups of microcode operations stored in a row may be included in the same microcode routine, or some of the groups may be included in different microcode routines.

Multiple control sequences per row of microcode ROM

A method and mechanism for performing division. A processor includes a divider configured to perform arithmetic division operations. Prior to dividing a dividend by a divisor, the divider manipulates the dividend and divisor to reduce the number of bits considered and the computations required to perform the division. The divisor is normalized by eliminating sign bits. The dividend is prescaled to eliminate one or more sign bits. Prescaling of the dividend may not be precise as sign bits of the dividend may be shifted out as groups of bits, rather than individual bits. Prescaling of the dividend may be adjusted to account for the fact that the divider considers multiple bits of the dividend at a time. Subsequent to prescaling and adjustment, the dividend may be adjusted in dependence upon the normalization of the divisor. Further adjustment may be utilized to maintain a significance relationship between the divisor and dividend. Subsequent to further adjustment, the division operation may be completed.

Fast hardware divider

A method and mechanism for performing shift operations using a shuffle unit. A processor includes a shuffle unit configured to perform shuffle operations responsive to shuffle instructions. The shuffle unit is adapted to support shift operations as well. In response to determining a shuffle instruction is received, selected bits of an immediate value of the shuffle instruction are used to generate byte selects for relocating bytes of a source operand. In response to determining the instruction is a shift instruction, the shuffle unit performs an arithmetic operation on a first and second value, where the first value corresponds to a particular destination byte position, and the second value corresponds to the immediate value. The result of the arithmetic operation comprises a byte select which selects one of the bytes of a source operand for conveyance to the particular destination byte position. In the event a destination byte position should be cleared by the shift operation, the output for the particular destination byte position is forced to zero.

Using a shuffle unit to implement shift operations in a processor

A cache system is constructed in accordance with an architecture that comprises a tag array into which tags are stored that are used to determine whether a hit or a miss into the cache system has occurred. Further, the cache system comprises a data array into which cache lines of data are stored, each cache line comprising a plurality of sub-lines, and each sub-line is adapted to be written back to a system memory separate from the other sub-lines. The cache system also comprises a controller coupled to the tag and data arrays. The tag array includes a cache-line dirty bit associated with each cache line and the data array includes a plurality of dirty bits for each cache line. The plurality of dirty bits comprises one sub-line dirty bit for each sub-line.

Organization of dirty bits for a write-back cache

A microprocessor including a level two cache memory including asynchronously accessible cache blocks. The microprocessor includes an execution unit coupled to a cache memory subsystem which includes a plurality of storage blocks, each configured to store a plurality of data units. Each of the plurality of storage blocks may be accessed asynchronously. In addition, the cache subsystem includes a plurality of tag units which are coupled to the plurality of storage blocks. Each of the tag units may be configured to store a plurality of tags each including an address tag value which corresponds to a given unit of data stored within the plurality of storage blocks. Each of the plurality of tag units may be accessed synchronously.

Microprocessor including bank-pipelined cache with asynchronous data blocks

A multiplier includes a plurality of subunits. Each of the plurality of subunits is configured to perform a portion of a multiplication operation, and the plurality of subunits are coupled together to perform the multiplication operation. At least a first subunit of the plurality of subunits and a second subunit of the plurality of subunits are configured to perform a same portion of the multiplication operation. The first subunit and the second subunit are clocked at a first clock frequency, during use, that is less than a second clock frequency at which a remainder of the plurality of subunits are clocked during use. The first subunit and the second subunit each have inputs coupled to a third subunit of the plurality of subunits to receive multiplication operations to be operated upon by the respective first subunit and second subunit.

Alternate phase dual compression-tree multiplier

Various methods and systems for implementing a sectored least recently used (LRU) cache replacement algorithm are disclosed. Each set in an N-way set-associative cache is partitioned into several sectors that each include two or more of the N ways. Usage status indicators such as pointers show the relative usage status of the sectors in an associated set. For example, an LRU pointer may point to the LRU sector, an MRU pointer may point to the MRU sector, and so on. When a replacement is performed, a way within the LRU sector identified by the LRU pointer is filled.

Sectored least-recently-used cache replacement

A system and method for transferring data using an early response signal to indicate subsequent transmission of data after a fixed latency, wherein the signal and data are transferred from a first clock domain to a second clock domain using a clock skipping technique. In one embodiment, an early response signal is transmitted by a first device k clock pulses prior to transmission of the data. The receiving device, which is operating at a higher clock rate, receives the early response signal and delays the signal by the number of skipped pulses which will occur in the second clock domain before the occurrence of the k valid pulse. The second device employs a skip pattern generator to generate a signal indicative of this number of skipped pulses and provides the number to a delay circuit which delays the early response signal for an this number of clock pulses. The delayed early response signal is then output to the appropriate logic to indicate the latency of the subsequent data transfer.

Method and apparatus to provide fixed latency early response in a system with multiple clock domains with fixable clock ratios

A cache controller configured to speculatively invalidate a cache line may respond to an invalidating request or instruction immediately instead of waiting for error checking to complete. In case the error checking determines that the invalidation is erroneous and thus should not be performed, the cache controller protects the speculatively invalidated cache line from modification until error checking is complete. This way, if the invalidation is later found to be erroneous, the speculative invalidation can be reversed. If error checking completes without detecting any errors, the speculative invalidation becomes non-speculative.

Method and system for speculatively invalidating lines in a cache

A processor is described which includes a stride detect table. The stride detect table includes one or more entries, each entry used to track a potential stride pattern. Additionally, each entry includes a confidence counter. The confidence counter may be incremented each time another address in the pattern is detected, and thus may be indicative of the strength of the pattern (e.g., the likelihood of the pattern repeating). At a first threshold of the confidence counter, prefetching of the next address in the pattern (the most recent address plus the stride) may be initiated. At a second, greater threshold, a more aggressive prefetching may be initiated (e.g. the most recent address plus twice the stride). In some implementations, the prefetch mechanism including the stride detect table may replace a prefetch buffer and prefetch logic in the memory controller.

Stride based prefetcher with confidence counter and dynamic prefetch-ahead mechanism

A system and method for transferring data from a first clock domain to a second clock domain wherein a clock skipping technique is employed to maintain the same level of data throughput in the transmitting and receiving domains. In one embodiment, a plurality of serial data values are received from a device in the first clock domain and are stored in a plurality of flip-flops. The data values are clocked into the flip-flops, one value per flip-flop, at a first clock rate corresponding to the first clock domain. After a value is stored in the last flip-flop, the cycle is repeated and the previously stored values are overwritten. The data values are retrieved from the flip-flops after the values have had time to stabilize, but before they are overwritten. The values are retrieved at a second clock rate corresponding to a second clock domain and are transferred to a device in the second clock domain. If the clock rate in the first clock domain is greater than the clock rate of the second clock domain, one or more of the first clock pulses is periodically skipped, according to a predetermined pattern based on the ratio of the clock rates. Thus, the number of data values stored over a period of time is equal to the value retrieved over that period. If the clock rate in the first clock domain is less than the clock rate in the second clock domain, pulses of the second clock signal are periodically skipped to equalize the number of values stored and the number retrieved.

Method to transfer data in a system with multiple clock domains using clock skipping techniques

A superscalar microprocessor implements a reorder buffer to support out-of-order execution of instructions. To reduce the time delay for identifying mispredicted instructions, prioritizing mispredicted instructions, canceling instructions subsequent to the mispredicted instruction and reading status information from the reorder buffer, the availability of an instruction tag, which identifies the instruction being executed, during the execution of the instruction is utilized. The reorder buffer receives the tag of the instruction issued to the functional unit. In parallel with the execution of the instruction, the reorder buffer generates hit masks identifying instructions to be canceled in the event of a mispredicted branch. In parallel, status information from the instruction (or instructions) being executed is selected from the reorder buffer and prioritization masks are generated. Therefore, if a mispredicted branch is detected, the instructions that need to be canceled can be readily identified and the instruction status information is readily available.

Growing community of inventors

Austin, TX, United States of America

Teik-Chung Tan