Altera Corporation

Teik Chuan Tan

Choi Phaik Chin

Kian Yong Tiu

A method includes receiving a first circuit design, deriving circuit design revisions based on the first circuit design, receiving revision information for each of the circuit design revisions that is output as a result of compilation of the circuit design revisions, extracting location information, timing information, or both for resources from the revision information, for each of the circuit design revisions, mapping the resources into a chip view based on the location information, the timing information, or both. The chip view includes a virtual visualization of an actual physical chip and the resources are mapped to their actual locations on the virtual visualization as they would be implemented on the actual physical chip. The method also includes generating the chip view of the circuit design revisions that displays a report specific to one or more properties of the circuit design revisions.

Growing community of inventors

Kulim, Malaysia

Teik Chuan Tan