Nec Electronics Corporation

Nec Corporation

Renesas Electronics Corporation

Teiichirou Nishizaka

Kohji Kanamori

Noriaki Kodama

Isao Katayama

Yoshihiro Matsuura

Kaoru Ishihara

Yasushi Harada

Naruaki Minenaga

Chihiro Oshita

Junichi Suzuki

Akio Toda

Shinji Fujieda

Yasuhide Den

Masazumi Ikebe

According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.

Semiconductor storage device, semiconductor device, and manufacturing method therefor

Semiconductor device of a charge storage type

A semiconductor memory device comprises diffusion regions, a floating gate, a third diffusion region, a selection gate electrode, and a control gate electrode that three-dimensionally crosses the selection gate electrode and extends in a direction orthogonal to the selection gate electrode are included. A channel formed immediately below the selection gate and which constitutes a passage connecting the two diffusion regions has a shape in a top view, including a first path extending in one direction, from one diffusion region, and a second path extending from the end of the first path to the other diffusion region in a direction orthogonal to a first direction.

Semiconductor memory device

A nonvolatile memory device includes source and drain regions formed in a semiconductor substrate, and an insulating film formed on a channel region between the source region and the drain region in the semiconductor substrate. The nonvolatile memory device also includes a dielectric film formed above the channel region to store electric charge, and a control gate formed on the dielectric film. Compressive stress in the channel region is equal to or less than 50 MPa.

Nonvolatile memory and nonvolatile memory manufacturing method

In a multivalued ROM device including a plurality of memory cells each for storing N (N=2, 3, . . . )-bit information, each bit of the N-bit information corresponds to one address.

High read speed multivalued read only memory device

Growing community of inventors

Kanagawa, Japan

Teiichirou Nishizaka