International Business Machines Corporation

Teh-Sen Jen

John Balyoz

Chi Shih Chang

Majid Ghafghaichi

John A Palmieri

Donald B Mooney

Barry C Fox

Algirdas J Gruodis

Wadie Faltas Mikhail

Master image chip organization technique or method

Disclosed are improved LSI semiconductor design structures termed 'Master Image Chip Organization Techniques'. Utilizing the technique provides increased density and optimized performance of semiconductor devices, circuits, and part number functions. In accordance with the disclosed Master Image Chip Organization Method the semiconductor chips are optimally structured to facilitate the maximum number of devices and circuits, and to facilitate fabrication of a wide variety of LSI part numbers. Essentially, none of the semiconductor surface is dedicated for signal and power wiring channels. A master image wiring structure is provided which resides over the semiconductor surface and beneath a power surface. In addition, the master image wiring structure provides a means for personalizing power and signal wiring for a multiple power surface structure. The combined master image structure provides a means for optimally allocating semiconductor area for devices, functional units (micro and macro) and signal and power wiring to facilitate improved density and performance.

Disclosed is an improved masterslice design technique including structure, wiring, and method of fabricating, to provide improved Large Scale Integrated Devices. In accordance with the improved masterslice technique a plurality of semiconductor chips are provided wherein essentially the entire semiconductor surface area of each chip is utilized to provide cells selectable to be personalized (wired). None of the semiconductor surface area is dedicated for wiring channels. The individual cell area and cell configuration is optimally arrived at to facilitate wiring the maximum number, if not all of the cells contained on each chip, whereby circuit density is materially improved and a wide variety LSI device part numbers may be readily fabricated.

LSI Semiconductor device and fabrication thereof

An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less than that of prior layouts. Each circuit includes a first device including an elongated impurity region and a set of other impurity regions either in, or in contiguous relationship with, the elongated region; to form a set of diode junctions. The elongated region is capable of containing a predetermined maximum number of the other impurity regions. A second device is located adjacent the narrow side of said first device. A first set of first level conductors extends over the elongated region orthogonally with respect to the elongated direction and are interconnected to selected ones of the other impurity regions. Another conductor is a second level atop the substrate is connected to an impurity region of the second device and extends substantially parallel to the elongated direction. For the most part, this conductor connects the second device with one of the conductors in the first set. The reference potential connections to each circuit are also made preferably by conductive channels running in the same direction. With respect to chip architecture, each logic circuit is of substantially identical identical geometric form and arranged in columnar arrays.

High density semiconductor circuit layout

An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less than that of prior layouts. Each circuit includes a first device including an elongated impurity region and a set of other impurity regions either in, or in contiguous relationship with, the elongated region to form a set of diode junctions. The elongated region is capable of containing a predetermined maximum number of the other impurity regions. A second device is located adjacent the narrow side of said first device. A first set of first level conductors extends over the elongated region orthogonally with respect to the elongated direction and are interconnected to selected ones of the other impurity regions. Another conductor in a second level atop the substrate is connected to an impurity region of the second device and extends substantially parallel to the elongated direction. For the most part, this conductor connects the second device with one of the conductors in the first set. The reference potential connections to each circuit are also made preferably by conductive channels running in the same direction. With respect to chip architecture, each logic circuit is of substantially identical geometric form and arranged in columnar arrays.

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Fishkill, NY, United States of America

Teh-Sen Jen