Kulicke & Soffa Holdings, Inc.

Enablence USA Components Inc.

Ted T Chen

Michael P Skinner

Wenhua Lin

Jacob Sun

HongZhen Wei

Ray Liang

David J Chazan

Jan I Strandberg

James L Lykins

Todd S Kaplan

A method of making a planar lightwave circuit (PLC) waveguide capable of being integrated with a surface-mounted component is presented. The method entails etching a silicon substrate to form a slanted wall, forming a nonreflective waveguide portion on the silicon substrate, and depositing a reflective layer on the slanted wall. Light travels through the nonreflective waveguide portion in substantially a first direction, and the light from the nonreflective waveguide portion strikes the reflective layer to be redirected in a second direction. The second direction may be the direction toward the surface-mounted component. A PLC waveguide device made with the above method is also presented.

Reflective planar lightwave circuit waveguide

A dielectric layer in a wiring substrate having a sloped sidewall. A photomask used to pattern the dielectric layer includes optical proximity features. The size and spacing of the optical proximity features are generally less than the resolution limit of the exposure tool used and do not print out on the layer. The optical proximity features provide a transition region between fully exposed material and un-exposed material, which results in a sloped sidewall of the photo-sensitive material after development. The sloped sidewall provides a more reliable thin film metal layer to contact through vias, and may be used to conserve wiring board area by allowing smaller via spacing.

Wiring substrate features having controlled sidewall profiles

A method for forming a planarized thin film dielectric film on a surface of a common circuit base upon which one or more integrated circuits are to be attached. The common circuit base includes raised features formed over its surface such that the raised features define a trench area between them. The method includes the steps of forming a first layer of the dielectric film over the common circuit base and over the raised features and the trench, then patterning the newly formed layer to remove portions of the layer formed over the raised features and expose the raised features. After the layer is patterned, formation of the dielectric film is completed by forming a second layer of the dielectric film over the patterned first layer. Additional film deposition and film patterning steps are performed to complete the layout of a thin film interconnect structure over said common circuit base, and an integrated circuit die is attached to the common circuit base and electrically connecting to the thin film interconnect structure. In a preferred embodiment, the first and second layers of the dielectric film are both formed from a photo-definable material and the patterning step includes exposing the first layer to light through a patterned mask corresponding to the raised features and developing the exposed layer with a developing solution to etch away portions of the first layer formed over the raised features.

Method of planarizing thin film layers deposited over a common circuit

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Saratoga, CA, United States of America

Ted T Chen