Hewlett-packard Company

Hewlett-packard Development Company, L.P.

Ted Scott Rakel

S Paul Tucker

Alan S Krech, Jr

Theodore G Rossin

Jon L Ashburn

Edmundo Rojas

Glenn W Strunk

Michael S McGrath

John G McBride

Douglas Shelborn Stirrett

DC margin of a latch of a circuit under design is determined by performing three simulations. A simulation is performed to find the trip voltage of the forwarding inverter of the latch. A second simulation is performed to find the one margin of the latch. Lastly, a third simulation is performed to find the zero margin of the latch. During each of the simulations to find the one margin and the zero margin, the worst case input signal path from the various driver circuit elements and signal paths within the circuit under design is determined analytically by accumulating weighted resistance of each of the circuit elements along the signal paths. The weights assigned to the circuit elements are empirically determined based on the topology configuration of each of the circuit elements, e.g., the type circuit element, the signal being passed through the circuit element and whether a threshold voltage drop occurs between the drive circuit element and the pass circuit element.

Method of determining DC margin of a latch

A method for reducing false electrical rule violations during the analysis of a digital circuit having mutually exclusive signal relationships therein. The use of designer knowledge about signals which are mutually exclusive in the circuit design is employed to determine, based on all relevant mutually exclusive signal relationships in the circuit design under test, all possible permutations of active signals used in the analysis. For each permutation, the analysis is performed using the active signals associated with the permutation while ignoring the effect of all signals that are inactive based on the mutually exclusive signal relationships. The invention may be applied to any digital circuit test wherein the effect of mutually exclusive signal relationships affects the outcome of the analysis.

Method for performing electrical rules checks on digital circuits with mutually exclusive signals

An Electrical Rules Check (ERC) methodology ensures the quality of an electrical circuit through the creation of up to four different data structures, corresponding to one or more nodes, one or more small nodes, one or more non-resistor elements, and one or more resistor elements of the circuit, that are used by an ERC program running on one or more processors. The creation of data structures for small nodes and resistor elements in which less information need be stored for use by the ERC program minimizes the amount of data storage that must be utilized.

Framework for rules checking utilizing resistor, nonresistor, node and small node data structures

The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed. A plurality of control unit logic elements correspond respectively with the control units and control instruction branching within their respective control unit by defining the next address field. A branch central intelligence mechanism controls branching between the control units by defining the next address field.

ROM-based control unit in a geometry accelerator for a computer graphics system

The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system by providing a branch central intelligence mechanism. Architecturally, the geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed. A plurality of control unit logic elements correspond respectively with the control units and control instruction branching within their respective control unit by defining the next address field. Finally, a branch central intelligence mechanism controls branching between the control units by defining the next address field.

Centralized branch intelligence system and method for a geometry accelerator

ROM-based control units in a geometry accelerator for a computer

A novel system and method computes a floating point value of an exponential expression in the form of 'a.sup.x ' in a geometry accelerator. In accordance with one aspect of the invention, the method includes the steps of receiving the values 'a' and x of the exponential expression, where both 'a' and x are represented in floating point format. As will be appreciated by those skilled in the art, the values will by supplied by software through an appropriate graphics application program interface (API). The method utilizes a mantissa value of the floating point representation of 'a' to index a first value in a first look-up table, the value being an approximation for log2(a). Then, the method multiplies the looked-up value by the value of x to obtain an intermediate result. This intermediate result is then partitioned into a fractional component and an integer component, wherein the fractional component is normalized/converted to floating point format. The method then utilizes a mantissa value of the floating point representation of the fractional component of the intermediate result to index a first value in a second look-up table, the value being an approximation for 2.sup.fract, where fract is the fractional component. Thereafter, the method computing 2.sup.integer, where integer is the integer component. This step may be directly computed by the math core of the geometry accelerator, since it is an integer exponent. Finally, the method multiplies the results of steps that compute the 2.sup.fract and 2.sup.integer values to obtain a final value. This final value is a close approximation of the exponential expression a.sup.x.

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Fort Collins, CO, United States of America

Ted Scott Rakel