Freescale Semiconductor,inc.

Motorola Corporation

Other

Paul Scherrer Institut

Garching Innovations Gmbh

Ted R White

Bich-Yen Nguyen

Mariam G Sadaka

Voon-Yew Thean

Alexander L Barr

Brian A Winstead

Marius K Orlowski

Olubunmi O Adetutu

Shawn George Thomas

Da Zhang

Victor H Vartanian

Chun-Li Liu

Alexander Barr

Dejan Jovanovic

Gowrishankar L Chindalore

Leo Mathew

Robert E Jones

Venkat Kolagunta

Zhonghai Shi

Brian J Goolsby

Jung-Hui Lin

Melissa O Zavala

Linda B McCormick

Colita M Parker

Gauri V Karve

Mark Douglas Hall

James David Burnett

Philip J Tobin

Tab Allen Stephens

Stanley Michael Filipiak

Gregory S Spencer

Bernard J Roman

John M Grant

Wayne M Paulson

Marius Orlowski

T P Ong

Matthew W Stoker

Daniel T Pham

Ting-Chen Hsu

Jing Liu

Anne M Vandooren

Bradley M Somero

Debby Eades

Qianghua Xie

Detlev Gruetzmacher

Jeff L Klein

Mark A Chonko

Lubomir Cergel

Shawn G Thomas

Peter Wennekers

Andreas A Wild

Oliver G Schmidt

Embodiments include a split-gate non-volatile memory cell that is formed having a control gate and a select gate, where at least a portion of the control gate is formed over the select gate. A charge storage layer is formed between the select gate and the control gate. The select gate is formed using a first conductive layer and a second conductive layer. The second conductive layer is formed over the first conductive layer and has a lower resistivity than the first conductive layer. In one embodiment, the first conductive layer is polysilicon and the second conductive layer is titanium nitride (TiN). In another embodiment, the second conductive layer may be a silicide or other conductive material, or combination of conductive materials having a lower resistivity than the first conductive layer.

Split-gate non-volatile memory cells having improved overlap tolerance

A method for forming a shared contact in a semiconductor device having a gate electrode corresponding to a first transistor and a source/drain region corresponding to a second transistor is provided. The method includes forming a first opening in a dielectric layer overlying the gate electrode and the source/drain region, wherein the first opening extends substantially to the gate electrode corresponding to the first transistor. The method further includes after forming the first opening, forming a second opening, contiguous with the first opening, in the overlying dielectric layer, wherein the second opening extends substantially to the source/drain region corresponding to the second transistor. The method further includes forming the shared contact between the gate electrode corresponding to the first transistor and the source/drain region corresponding to the second transistor by filling the first opening and the second opening with a conductive material.

Method of forming a shared contact in a semiconductor device

An electronic device can include a first transistor having a first channel region further including a heterojunction region that, in one aspect, is at most approximately 5 nm thick. In another aspect, the first transistor can include a p-channel transistor including a gate electrode having a work function mismatched with the associated channel region, and the heterojunction region can lie along a surface of a semiconductor layer closer to a substrate than an opposing surface of the substrate. The electronic device can also include an n-channel transistor, and the subthreshold carrier depth of the p-channel and n-channel transistors can have approximately a same value as compared to each other. A process of forming the electronic device can include forming a compound semiconductor layer having an energy band gap greater than approximately 1.2 eV.

Electronic device including a heterojunction region

A method for forming a split-gate non-volatile memory (NVM) cell includes forming a first gate layer over a semiconductor substrate; forming a conductive layer over the first gate layer; patterning the first gate layer and the conductive layer to form a first sidewall, wherein the first sidewall comprises a sidewall of the first gate layer and a sidewall of the conductive layer; forming a first dielectric layer over the conductive layer and the semiconductor substrate, wherein the first dielectric layer overlaps the first sidewall; forming a second gate layer over the first dielectric layer, wherein the second gate layer is formed over the conductive layer and the first gate layer and overlaps the first sidewall; and patterning the first gate layer and the second gate layer to form a first gate and a second gate, respectively, of the split-gate NVM cell, wherein the second gate overlaps the first gate and a portion of the conductive layer remains between the first gate and the second gate.

Split-gate non-volatile memory cell having improved overlap tolerance and method therefor

A semiconductor process and apparatus includes forming first and second metal gate electrodes () over a hybrid substrate () by forming the first gate electrode () over a first high-k gate dielectric () and forming the second gate electrode () over at least a second high-k gate dielectric () different from the first gate dielectric (). By forming the first gate electrode () over a first SOI substrate () formed by depositing (100) silicon and forming the second gate electrode () over an epitaxially grown (110) SiGe substrate (), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes () having improved hole mobility.

Modified hybrid orientation technology

A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.

Method for making a semiconductor structure using silicon germanium

A non-volatile memory cell including a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region is provided. The non-volatile memory cell further includes a select gate structure overlying a first portion of the channel region. The non-volatile memory cell further includes a control gate structure formed overlying a second portion of the channel region, wherein the control gate structure includes a nanocrystal stack having a height, wherein the control gate structure has a convex shape in a corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a side surface of the control gate structure, wherein a ratio of radius of the control gate structure in the corner region to the height of the nanocrystal stack is at least 0.5.

Split gate non-volatile memory cell with improved endurance and method therefor

An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

Electronic devices including a semiconductor layer

A wafer having a silicon layer that is strained is used to form transistors. The silicon layer is formed by first forming a silicon germanium (SiGe) layer of at least 30 percent germanium that has relaxed strain on a donor wafer. A thin silicon layer is epitaxially grown to have tensile strain on the relaxed SiGe layer. The amount tensile strain is related to the germanium concentration. A high temperature oxide (HTO) layer is formed on the thin silicon layer by reacting dichlorosilane and nitrous oxide at a temperature of preferably between 800 and 850 degrees Celsius. A handle wafer is provided with a supporting substrate and an oxide layer that is then bonded to the HTO layer. The HTO layer, being high density, is able to hold the tensile strain of the thin silicon layer. The relaxed SiGe layer is cleaved then etched away to expose the thin silicon layer. A low temperature silicon layer is then epitaxially grown with tensile strain, correlated to the tensile strain of the thin silicon layer, on the thin silicon layer using trisilane at a temperature preferably not in excess of 500 degrees Celsius. The resulting tensile strain, correlated to the strain of the thin silicon layer, is thus also correlated to the germanium concentration of the relaxed SiGe layer. The thickness of the low temperature silicon layer, using the trisilane at low temperature, is significantly greater than what would normally be expected for a silicon layer of that tensile strain.

Method for forming a semiconductor structure having a strained silicon layer

A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer () that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer () by a buried insulator layer (); forming an STI region () in the second semiconductor layer () and buried insulator layer (); exposing the first semiconductor layer () in a first area () of a STI region (); epitaxially growing a first epitaxial semiconductor layer () from the exposed first semiconductor layer (); and selectively etching the first epitaxial semiconductor layer () and the second semiconductor layer () to form CMOS FinFET channel regions (e.g.,) and planar channel regions (e.g.,) from the first epitaxial semiconductor layer () and the second semiconductor layer ().

Twisted dual-substrate orientation (DSO) substrates

A transistor having a source with higher resistance than its drain is optimal as a pull-up device in a storage circuit. The transistor has a source region having a source implant having a source resistance. The source region is not salicided. A control electrode region is adjacent the source region for controlling electrical conduction of the transistor. A drain region is adjacent the control electrode region and opposite the source region. The drain region has a drain implant that is salicided and has a drain resistance. The source resistance is more than the drain resistance because the source region having a physical property that differs from the drain region.

Transistor with asymmetry for data storage circuitry

Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.

Semiconductor device structure

A semiconductor process and apparatus provides a planarized hybrid substrate () by removing a nitride mask layer () and using an oxide polish stop layer () when an epitaxial semiconductor layer () is being polished for DSO and BOS integrations. To this end, an initial SOI wafer semiconductor stack () is formed which includes one or more oxide polish stop layers () formed between the SOI semiconductor layer () and a nitride mask layer (). The oxide polish stop layer () may be formed by depositing a densified LPCVD layer of TEOS to a thickness of approximately 100-250 Angstroms.

Step height reduction between SOI and EPI for DSO and BOS integration

A substrate includes a first region and a second region. The first region comprises a III-nitride layer, and the second region comprises a first semiconductor layer. A first transistor (such as an n-type transistor) is formed in and on the III-nitride layer, and a second transistor (such as a p-type transistor) is formed in and on the first semiconductor layer. The III-nitride layer may be indium nitride. In the first region, the substrate may include a second semiconductor layer, a graded transition layer over the second semiconductor layer, and a buffer layer over the transition layer, where the III-nitride layer is over the buffer layer. In the second region, the substrate may include the second semiconductor layer and an insulating layer over the second semiconductor layer, where the first semiconductor layer is over the insulating layer.

Integrated circuit with different channel materials for P and N channel transistors and method therefor

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Austin, TX, United States of America

Ted R White