Telefonaktiebolaget Lm Ericsson (publ)

Infineon Technologies Ag

Ericsson Gmbh

Ted Johansson

Larry C Leighton

Hans Norstr&ouml;m

Hans Norström

Carl Bj&ouml;rmander

Jose-Maria Gobbi

Torkel Bengt Arnborg

Hans Norstroem

Erik G Larsson

Ulf Gustavsson

Anders Lindgren

Andrej Litwin

Stefan Sahl

Arne O Rydin

Ivar Hamberg

Bengt T Arnborg

Bertil Skoglund

Jan-Christian Nystr&ouml;m

Christian Nyström

Carl BJÖRMANDER

The present disclosure relates to a system () for wireless reference signal distribution. The system () comprises an antenna array () comprising a plurality of transceivers (). The antenna array () is arranged to transmit and receive a in radio signal via the plurality of transceivers (). The system () further comprises a synchronization signal generator () arranged to transmit wirelessly at least one synchronization signal. Each synchronization signal comprises at least one time-dependent signal component, wherein the at least one synchronization signal has at least one time-dependent signal component with an amplitude above a predetermined threshold during a total duration of the at least one synchronization signal. Each transceiver () is connected to a respective synchronization signal receiver () arranged to receive the at least one synchronization signal. The synchronization signal receiver () is arranged to generate a reference signal for the respective transceiver () based on the received at least one synchronization signal. The present disclosure also relates to corresponding methods and computer programs.

Wireless reference signal distribution

A method for fabrication of a monolithically integrated SOI substrate capacitor has the steps of: forming an insulating trench, which reaches down to the insulator and surrounds a region of the monocrystalline silicon of a SOI structure, doping the monocrystalline silicon region, forming an insulating, which can be nitride, layer region on a portion of the monocrystalline silicon region, forming a doped silicon layer region on the insulating layer region, and forming an insulating outside sidewall spacer on the monocrystalline silicon region, where the outside sidewall spacer surrounds the doped silicon layer region to provide an isolation between the doped silicon layer region and exposed portions of the monocrystalline silicon region. The monocrystalline silicon region, the insulating layer region, and the doped silicon layer region constitute a lower electrode, a dielectric, and an upper electrode of the capacitor.

Method for fabrication of a capacitor, and a monolithically integrated circuit comprising such a capacitor

A method in the fabrication of an integrated circuit including a PMOS varactor and an npn transistor, comprises the steps of (i) simultaneously forming buried n-doped regions () for the PMOS varactor and the npn transistor in a p-doped substrate (); (ii) simultaneously forming n-doped wells () above the buried n-doped regions (); (iii) simultaneously forming field isolation areas () around the n-doped regions (); (iv) forming a PMOS gate region () and a p-doped base each in a respective one of the n-doped wells (); and (v) simultaneously forming n-doped contacts to the buried n-doped regions (); the contacts being separated from the n-doped wells (). Source and drain regions may be formed in the PMOS n-well (inversion mode) or the PMOS n-doped contact may be formed in the PMOS n-well instead of being separated from there (accumulation mode).

Semiconductor process and PMOS varactor

A method in the fabrication of a monolithically integrated vertical device on an SOI substrate comprises the steps of providing an SOI substrate including, from bottom to top, a silicon bulk material, an insulating layer, and an monocrystalline silicon layer; forming an opening in the substrate, which extends into the bulk-material, forming silicon oxide on exposed silicon surfaces in the opening and subsequently removing the formed oxide, whereby steps in the opening are formed; forming a region of epitaxial silicon in the opening; and forming a deep trench in an area around the opening, whereby the steps in the opening are removed.

Method in the fabrication of a monolithically integrated vertical device on an SOI substrate

A method for fabrication of a monolithically integrated SOI substrate capacitor has the steps of: forming an insulating trench (), which reaches down to the insulator () and surrounds a region () of the monocrystalline silicon () of a SOI structure, doping the monocrystalline silicon region, forming an insulating, which can be nitride, layer region () on a portion of the monocrystalline silicon region, forming a doped silicon layer region () on the insulating layer region (), and forming an insulating outside sidewall spacer () on the monocrystalline silicon region, where the outside sidewall spacer surrounds the doped silicon layer region to provide an isolation between the doped silicon layer region and exposed portions of the monocrystalline silicon region. The monocrystalline silicon region ('), the insulating layer region (&#x2032;), and the doped silicon layer region () constitute a lower electrode, a dielectric, and an upper electrode of the capacitor.

A method in the fabrication of an IL circuit comprises (i) forming a common base of a lateral bipolar transistor and emitter of a vertical bipolar multicollector transistor, a common collector of the lateral transistor and base of the vertical multicollector transistor, and an emitter of the lateral transistor in a substrate; (ii) forming, from a first deposited polycrystalline layer, a contact region for the common collector/base and a contact region for the emitter of the lateral transistor; (iii) forming an isolation structure for electric isolation of the polycrystalline contact region for the common collector/base; and (iv) forming, from a second deposited polycrystalline layer, a contact region for the common base/emitter and multiple collectors of the vertical multicollector transistor.

Method in the fabrication of an integrated injection logic circuit

A method in the fabrication of an integrated bipolar circuit comprises the steps of: providing a p-type substrate; forming in the substrate a buried n+-type region and an n-type region above the buried n-type region; forming field isolation areas around the n-type region; forming a PMOS gate region on the n-type region; forming a diffused n-type contact from the upper surface of the substrate to the buried n-type region; the contact being separated from the n-type region; forming a p-type polysilicon source on the n-type region; forming a p-type source in the n-type region; forming a p-type drain in the n-type region; and connecting the PMOS transistor structure to operate as a PNP transistor, wherein the source is connected to the gate and constitutes an emitter of the PNP transistor; the drain constitutes a collector of the PNP transistor; and the n-type region constitutes a base of the PNP transistor.

Semiconductor fabrication process, lateral PNP transistor, and integrated circuit

A monolithically integrated circuit comprises a thin film resistor () with low resistance and low temperature coefficient; a high frequency lateral power transistor device () including gate (), source () and drain () regions, and a Faraday shield layer region (') above the gate region; and at least a first metallization layer () there above for electrical connection of the gate (), source () and drain () regions through via holes filled with conductive material (). The thin film resistor () and the Faraday shield layer region (&#x2032;) are made in the same conductive layer, which is arranged below the first metallization layer ().

Monolithically integrated circuit comprising a thin film resistor, and fabrication method thereof

A method in the fabrication of an integrated bipolar circuit for forming a p/n-junction varactor is disclosed. The method featuring the steps of providing a p-doped substrate (); forming a buried n-doped region () in the substrate; forming in the substrate an n-doped region () above the buried n-doped region (); forming field isolation () around the n-doped region (); multiple ion implanting the n-doped region (); forming a p-doped region () on the n-doped region (); forming an n-doped contact region to the buried n-doped region (), the contact region being separated from the n-doped region (); and heat treating the hereby obtained structure to set the doping profiles of the doped regions. The multiple ion implantation of the n-doped region (); the formation of the p-doped region (); and the heat treatment are performed to obtain a hyper-abrupt p/n-junction within the n-doped region ().

Fabrication method, varactor, and integrated circuit

A method in the fabrication of a silicon-germanium mesa transistor in a semiconductor process flow comprises the steps of providing a p-type doped silicon bulk substrate () having an n-type doped surface region () being a subcollector; depositing epitaxially thereon a silicon layer () comprising n-type dopant; depositing epitaxially thereon a silicon layer () comprising germanium and p-type dopant; forming in the epitaxial layers () field isolation areas () around, in a horizontal plane, a portion of the epitaxial layers () to simultaneously define an n-type doped collector region () on the subcollector (); a p-type doped base region () thereon; and an n-type doped collector plug on the subcollector (), but separated from the n-type doped collector region () and the p-type doped base region (); and forming in the p-type doped base region () an n-type doped emitter region.

Silicon-germanium mesa transistor

The present invention relates to a semiconductor device arranged at a surface of a semiconductor substrate having an initial doping having an electrical connection comprising at least one plug made of a material with a high conductivity, especially a material other than the substrate, especially a metal plug, between said initially doped substrate and said surface of the substrate. The device has at least one ground connection arranged to be connected to a ground pin on a package. The ground connection is arranged to be connected to said ground pin using said electrical connection, where the initially doped substrate is arranged to be connected to said ground pin via a reverse side of the substrate, opposite said surface, and thereby being arranged to establish a connection between said ground connection and said ground pin.

Semiconductor device with deep substrates contacts

In a bipolar double-poly transistor comprising a layer of base silicon (') on a silicon substrate (&#x2032;), a first layer of silicon dioxide (&#x2032;) on the base silicon layer (&#x2032;), an emitter window (&#x2032;) extending through the first layer (&#x2032;) of silicon dioxide and the base silicon layer (&#x2032;), a second layer (&#x2032;) of silicon dioxide in the emitter window (&#x2032;), silicon nitride spacers (&#x2032;) on the second layer (&#x2032;) of silicon dioxide in the emitter window (&#x2032;), and emitter silicon (&#x2032;) in the emitter window (&#x2032;), an isolating silicon nitride seal is provided to separate the base silicon (&#x2032;) from the emitter silicon (&#x2032;) to prevent short-circuiting between the base silicon (&#x2032;) and the emitter silicon (&#x2032;) in the transistor.

Arrangement for preventing short-circuiting in a bipolar double-poly transistor and a method of fabricating such an arrangement

At the surface of a substrate a gate oxide layer is produced and is given a dual thickness. A first oxide layer is produced over the surface of a substrate by thermal oxidation and is covered by a mask layer defining suitably located openings. A material accelerating or retarding the oxidation of the substrate is ion implanted through the first oxide layer in the openings, after which the mask is removed and the thermal oxidation is continued over the now exposed total surface of the first oxide layer. The material used for ion implanting can be an oxidation rate promoting material such as chloride and bromine. The manufacturing method is simple and adds little to presently used process flows for fabricating MOS devices. The dual thickness of the gate oxide gives the manufactured MOS device a low level of total noise generated when using the device for instance in RF-circuits.

Manufacturing of a low-noise mos device

A method for selective etching in the manufacture of a semiconductor device comprises: forming a layer () of silicon-germanium on a substrate () of monocrystalline silicon or on a substrate at least comprising a surface layer of monocrystalline silicon, depositing at least a dielectric layer () on the silicon-germanium layer () and patterning the resultant structure (), whereafter the dielectric layer () and the silicon-germanium layer () are etched away within a predetermined region (). Preferably, the silicon-germanium layer () is amorphous, whereby the dielectric layer () is deposited on the amorphous silicon-germanium layer () in such a manner to prevent crystallization of the amorphous layer. After etching the structure may be heat-treated such that the amorphous layer crystallizes. The method is preferably applicable for etching an emitter window in the manufacture of a bipolar transistor having a self-registered base-emitter structure.

Selective base etching

A method for forming an electrical device structure in an integrated circuit comprises providing a substrate; forming a passivation layer thereon; forming a plurality of through holes in the passivation layer, the through holes; removing substrate material under the passivation layer by means of isotropic etching, thus forming at least a first cavity in the substrate beneath the plurality of through holes; forming a dielectric layer on top of the passivation layer to plug the through holes, thereby creating a membrane; and creating an electrical device, such as e.g. an inductor, above the membrane.

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Djursholm, Sweden

Ted Johansson