Hal Computer Systems, Inc.

Ted E Williams

Robert K Montoye

Michael A Shenoy

Skeet target

Asynchronous combinatorial logic apparatus and method are provided that propagate data through a logic array at the speed of a raw combinational logic array and generate a functional output signal. The apparatus and method provide a minimum expected value of data propagation delay. In one embodiment, a particular data path is identified that has higher than average usage probability based on knowledge of the probabalistic distribution of data values, and the particular data path connecting devices located in the identified higher usage path are modified, such as by shortening the path, so that the path that is known to have a higher usage is made faster. In another embodiment of a device implementing a combinational logic array needing a theoretical plurality of stages for executing the function is implemented with an asynchronous ring including a plurality of connected circuit stages wherein the plurality of stages is a smaller number of stages than the number of the theoretical plurality of stages, control logic for controlling the execution timing of the plurality of stages so that at least one of the plurality of stages executes more than once during the execution of the function, the apparatus thereby implements the theoretical plurality of stages in a smaller number of physical stages. In this manner, the apparatus achieves the performance of the larger combinational array having the theoretical plurality of stages in the smaller physical device area needed to implement the smaller number of circuit stages.

Self-timed logic circuit having zero-latency overhead and method for

A pullup circuit having a limited voltage swing and fast pullup and pulldown times comprises a pullup structure, a pulldown structure and an internal node. The pullup circuit operates to limit the current of the pullup structure before the N-tree discharges the internal node, thereby reducing the pullup effect of the pullup structure to reduce fall time and power consumption. Then the pullup circuit maximizes the current of the pullup structure after the N-tree has pulled down the internal node to increase the pullup effect of the pullup structure to reduce rise time. As a result, the voltage of the internal node both charges more quickly when the N-tree becomes inactive and discharges more quickly when the N-tree becomes active.

Fast swing-limited pullup circuit

A novel third phase of CMOS domino logic is identified and used in the logic system of the present invention to store data. The use of this third phase in addition to the normally used precharge and logic evaluation phases, provides a logic structure of cascaded domino logic gates which are pipelined without intervening latches for memory storage. The memory storage function of the conventional latches being provided by the third logic phase. The novel approach requires that the functional inputs to this system have strictly monotonic transitions during the logic evaluation phase, and requires that the precharge signal must be active during only the precharge phase. Embodiments of the pipelined system according to the invention, are structured so that the output of the pipeline are fed back to the input of the pipeline to form an iterative structure. Such a feedback pipeline is viewed as a 'loop' or 'ring' of logic. The logic ring circulates data until the entire computation is complete. A method for using the logic structure is also described.

Zero latency overhead self-timed iterative logic structure and method

A structure of logic gates, partial product circuits, and a multiplier tree is described for multiplying of two operands which may contain denormalized numbers in the same amount of time as needed to multiply normalized numbers. The generation of the most significant bits ('hidden bits') of the significands of the operands from the operand exponents, and the production of the partial products that are dependent on these hidden bits, is accomplished in parallel with the generation of the partial products of the expressed bits of the significands of the operands and the first level of the multiplier tree. The fraction field partial products are input into the top level of a multiplier tree comprised of various order adders and wires. The hidden bit partial products are then input into the body of the multiplier tree instead of the top level. Additional adders are allocated to accommodate these additional inputs, but without lengthening the longest serial path from the top to the bottom of the multiplier tree. The result of the multiplier tree is summed and output. The parallel processing arrangement allows the identification and multiplication of denormalized numbers without any added delay due to the generation of the hidden bits.

Method and apparatus for multiplying denormalized binary floating point

A multiplier tree sums the partial products of a multiplication operation, employing a regular hierarchical arrangement of bit adders that accept nine initial inputs and a carry input and produce three outputs and a carry output. The regularity of the structure of the bit adder allows it be used to form an array of bit adders to sum twenty-seven input bits and ten carry input bits to produce three output bits and ten carry outputs bits. These bit adders form the basis of the multiplier tree. The multiplier tree using this structure can sum the partial products from a 52 to 54 bit multiply operation in no more adder delays than a Wallace tree, but with a more regular structure. A method for reducing nine input signals to three output signals segregates the input signals into sets of signals and combines them into reduced sets of logically equivalent signals.

Multiplier tree using nine-to-three adders

Apparatus and methods for early quotient completion in arithmetic division include a quotient digit generator, one or more asynchronous shift registers and a remainder comparison block. As quotient digits are generated, each digit is transferred to a different asynchronous shift register in turn. Digits are immediately propagated down each shift register to the next most significant digit position. During propagation digits are also repeated at all lesser significant digit positions. At the end of a digit generation cycle, when all asynchronous shift registers have received one new digit, the remainder comparison block determines if the current remainder is the same as the last period's remainder. If not, the remainder comparison block sends a reset signal to all the shift registers, sending reset spacers along each register that reset all duplicate versions of the last digits sent. The registers are then ready to receive next period's series of quotient digits. If the remainders are the same, the remainder comparison block halts any further quotient digit generation. Connections from each cell of the shift registers are interleaved to produce a final quotient answer that is already both correctly aligned, and has all repeating digits available and in place.

Method and apparatus for early quotient completion in arithmetic division

CMOS domino logic is normally used only in two phases: precharge and logic evaluation. The invention uses a third phase to store data, which allows domino logic gates to be cascaded and pipelined without intervening latches. The inputs to this system must have strictly monotonic transitions during the logic evaluation phase and the precharge signal must be active during only the precharge phase. Furthermore, the pipelined system can feed its output back to the input to form an iterative structure. Such a feedback pipeline is viewed as a 'loop' or 'ring' of logic which circulates data until the entire computation is complete.

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Santa Clara County, CA, United States of America

Ted E Williams